xenia-rs/migration/project-root/ppc-manual/vmx/vcfux.md

vcfux — Vector Convert from Unsigned Fixed-Point Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000030a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcfu	vcfux	—	Vector Convert from Unsigned Fixed-Point Word

Syntax

vcfux [VD], [VB], [UIMM]

Encoding

vcfux — form VX

• Opcode word: 0x1000030a
• Primary opcode (bits 0–5): 4
• Extended opcode: 778
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vcfux: read	Source B vector register.
UIMM	vcfux: read	16-bit unsigned immediate. Zero-extended.
VD	vcfux: write	Destination vector register.

Register Effects

vcfux

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcfux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcfux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:518
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:93
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:502
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4314-4321

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcfux => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = crate::vmx::cvt_u32_to_f32(b[i], uimm); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Convert unsigned-Q uint32 lane to binary32. For each of the four word lanes, VD[i] = (float)VB[i] / 2^UIMM. The 5-bit UIMM (bits 11..15) gives the Q-format fractional shift, in 0..31.
• Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Use case. Unsigned Q-format fixed-point → IEEE float; common for normalised colour channels (vcfux vD, vColor, 8 rescales 0..255 to 0..0.996).
• Inexact rounding. Magnitudes above 2^24 lose precision. Default rounding is round-to-nearest-even; VMX has no per-instruction rounding control.
• VSCR[NJ] affects sub-normal outputs. Xenia's crate::vmx::cvt_u32_to_f32 honours the architectural snapshot.
• No VSCR[SAT], no XER changes, no exceptions.
• No VMX128 sibling.
• Round-trip caveat. Pair with vctuxs for the inverse — but the inverse saturates rather than wraps, so floats above 2^32 − 1 clamp to 0xFFFFFFFF and stick VSCR[SAT].

Related Instructions

• vcfsx — same shape, signed source.
• vctuxs — inverse: float → unsigned-Q uint32 with saturation.
• vctsxs — inverse: float → signed-Q int32 with saturation.
• vrfin, vrfiz — float-to-integer rounding modes for the un-scaled case.

IBM Reference

• AIX 7.3 — vcfux (Vector Convert from Unsigned Fixed-Point Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions