xenia-rs/migration/project-root/ppc-manual/vmx/vmhraddshs.md

vmhraddshs — Vector Multiply-High Round and Add Signed Signed Half Word Saturate

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000021

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmhraddshs	vmhraddshs	—	Vector Multiply-High Round and Add Signed Signed Half Word Saturate

Syntax

vmhraddshs [VD], [VA], [VB], [VC]

Encoding

vmhraddshs — form VA

• Opcode word: 0x10000021
• Primary opcode (bits 0–5): 4
• Extended opcode: 33
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmhraddshs: read	Source A vector register.
VB	vmhraddshs: read	Source B vector register.
VC	vmhraddshs: read	Source C vector register / 3-bit selector.
VD	vmhraddshs: write	Destination vector register.
VSCR	vmhraddshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vmhraddshs

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vmhraddshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmhraddshs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmhraddshs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:888
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:102
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:577
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3534-3548

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmhraddshs => {
            // Rounded multiply-add: (vA[i]*vB[i] + 0x4000) >> 15 + vC[i], saturating.
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let c = crate::vmx::as_i16x8(ctx.vr[instr.rc()]);
            let mut r = [0i16; 8]; let mut sat = false;
            for i in 0..8 {
                let prod = (a[i] as i32 * b[i] as i32 + 0x4000) >> 15;
                let (v, s) = crate::vmx::sat_i32_to_i16(prod + c[i] as i32);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Rounded Q15 fixed-point multiply-add, saturating. Eight half-word lanes; per lane:

  prod  = (int16(VA[i]) * int16(VB[i]) + 0x4000) >> 15   ; round half-up
  VD[i] = clamp(prod + int16(VC[i]), -32768, +32767)
  

  Identical to vmhaddshs except for the +0x4000 rounding bias before the shift.
• Half-up rounding to even-magnitude. The +0x4000 bias rounds the discarded low 15 bits toward the nearest representable value, with ties broken away from zero. For most DSP work this is the desired behaviour and gives lower mean error than the truncating variant.
• VSCR[SAT] is sticky-set if the final sum overflows int16. The rounding bias can itself push a lane that was at +32767 past the cap — important for tight Q15 audio where the truncating form might not have saturated.
• Same 0x8000 * 0x8000 >> 15 gotcha as vmhaddshs: the product is +32768.5 rounded to +32769, which still saturates.
• Big-endian half lanes. Lane 0 is the most-significant half.
• No XER changes, no exceptions.
• No VMX128 sibling.
• Common usage. High-quality Q15 audio filter taps where round-toward-nearest is preferred over truncate-toward-zero.

Related Instructions

• vmhaddshs — same op without the rounding bias.
• vmladduhm — same shape, modulo (no shift, no saturate), unsigned.
• vmsumshs, vmsumshm — multiply-sum across pairs of lanes.
• vaddshs, vmaxsh — saturating add and max at same lane width.

IBM Reference

• AIX 7.3 — vmhraddshs (Vector Multiply-High Round and Add Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Add Family