xenia-rs/migration/project-root/ppc-manual/vmx/vmladduhm.md

vmladduhm — Vector Multiply-Low and Add Unsigned Half Word Modulo

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000022

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmladduhm	vmladduhm	—	Vector Multiply-Low and Add Unsigned Half Word Modulo

Syntax

vmladduhm [VD], [VA], [VB], [VC]

Encoding

vmladduhm — form VA

• Opcode word: 0x10000022
• Primary opcode (bits 0–5): 4
• Extended opcode: 34
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmladduhm: read	Source A vector register.
VB	vmladduhm: read	Source B vector register.
VC	vmladduhm: read	Source C vector register / 3-bit selector.
VD	vmladduhm: write	Destination vector register.

Register Effects

vmladduhm

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmladduhm

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmladduhm"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:951
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:104
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:578
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3549-3560

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmladduhm => {
            // Multiply-low add (modulo): vD[i] = u16(vA[i] * vB[i] + vC[i]).
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let c = ctx.vr[instr.rc()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 {
                r[i] = a[i].wrapping_mul(b[i]).wrapping_add(c[i]);
            }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Modulo multiply-low add. Eight half-word lanes; per lane:

  VD[i] = (uint16(VA[i]) * uint16(VB[i]) + uint16(VC[i])) mod 2^16
  

  Only the low 16 bits of the 32-bit product survive — the "ml" in the mnemonic = "multiply low" (versus vmh* for "multiply high"). This is the fastest of the multiply-add family because nothing saturates and nothing rounds.
• Sign-agnostic. Modulo multiply for signed int16 and unsigned u16 is bit-identical at the low 16 bits, so this single instruction serves both.
• No VSCR[SAT] change. Wrap is silent.
• No XER, no exceptions.
• Big-endian half lanes. Lane 0 is the most-significant half.
• Aliasing legal. vmladduhm v3, v3, v4, v3 is the standard accumulate idiom (same register as both VA and VC).
• No VMX128 sibling.
• Common usage. Stride / index computation in vector loops, RGBA8 component recombination after a vupkhsb, per-element polynomial evaluation at half precision.

Related Instructions

• vmhaddshs — saturating high-half signed multiply-add (Q15).
• vmhraddshs — same, with rounding.
• vmsumuhm, vmsummbm — multiply-sum across pairs of lanes.
• vadduhm, vmaxuh — companion modulo / max ops at half width.

IBM Reference

• AIX 7.3 — vmladduhm (Vector Multiply-Low and Add Unsigned Half Word Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Add Family