xenia-rs/migration/project-root/ppc-manual/vmx/vmuleuh.md

vmuleuh — Vector Multiply Even Unsigned Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000248

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmuleuh	vmuleuh	—	Vector Multiply Even Unsigned Half Word

Syntax

vmuleuh [VD], [VA], [VB]

Encoding

vmuleuh — form VX

• Opcode word: 0x10000248
• Primary opcode (bits 0–5): 4
• Extended opcode: 584
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmuleuh: read	Source A vector register.
VB	vmuleuh: read	Source B vector register.
VD	vmuleuh: write	Destination vector register.

Register Effects

vmuleuh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmuleuh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmuleuh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1101
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:108
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:485
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3485-3492

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmuleuh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = a[2 * i] as u32 * b[2 * i] as u32; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Even-lane half-word multiply. Only half-word lanes 0, 2, 4, 6 of VA and VB participate (big-endian indexing). Each 16×16 unsigned product widens to an unsigned 32-bit word and is written to the corresponding word lane of VD. The odd half-words are ignored.
• Lane-count reduction. 8 half-word input lanes → 4 word output lanes. Pairing is VD.w[i] = VA.h[2*i] * VB.h[2*i] for i ∈ 0..3.
• No overflow possible. 0xFFFF * 0xFFFF = 0xFFFE0001 — fits in 32 bits. VSCR[SAT] is untouched.
• Pair with vmulouh to multiply every half-word lane. Interleave the two vectors with vmrghw/vmrglw (word-granularity) to rebuild the full element order, or feed both into vmsumuhm variants.
• No Rc, no XER, no FPSCR.
• No VMX128 sibling. Xenon code that needs 16-bit lane multiplies usually goes through vmsumuhm / vmsumuhs.

Related Instructions

• vmulouh — odd-half-word twin.
• vmulesh, vmulosh — signed-half-word even/odd.
• vmuleub, vmuloub — byte-granularity even/odd (→ half-word lanes).
• vmsumuhm, vmsumuhs — fused multiply-sum unsigned-half-word (modulo / saturating).
• vmrghw, vmrglw — interleave results.

IBM Reference

• AIX 7.3 — vmuleuh (Vector Multiply Even Unsigned Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic