xenia-rs/migration/project-root/ppc-manual/vmx/vmuleub.md

vmuleub — Vector Multiply Even Unsigned Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000208

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmuleub	vmuleub	—	Vector Multiply Even Unsigned Byte

Syntax

vmuleub [VD], [VA], [VB]

Encoding

vmuleub — form VX

• Opcode word: 0x10000208
• Primary opcode (bits 0–5): 4
• Extended opcode: 520
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmuleub: read	Source A vector register.
VB	vmuleub: read	Source B vector register.
VD	vmuleub: write	Destination vector register.

Register Effects

vmuleub

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmuleub

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmuleub"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1096
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:108
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:478
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3453-3460

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmuleub => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[2 * i] as u16 * b[2 * i] as u16; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Even-lane multiply. Only the even-indexed bytes of VA and VB participate — lanes 0, 2, 4, 6, 8, 10, 12, 14 (big-endian indexing, MSB-first). Each unsigned-byte × unsigned-byte product widens to an unsigned 16-bit half-word and is written to the corresponding half-word of VD. The odd lanes are ignored.
• Lane-count reduction. Input has 16 byte lanes; output has 8 half-word lanes. The pairing is VD.h[i] = VA.b[2*i] * VB.b[2*i] for i ∈ 0..7.
• No overflow possible. 8-bit × 8-bit unsigned ≤ 0xFF * 0xFF = 0xFE01, which fits in 16 bits. VSCR[SAT] is not touched; this is a modulo-equivalent op even though no modulo is needed.
• Pair with vmuloub to get all 16 products. Software that wants every byte × byte product typically issues vmuleub + vmuloub and then interleaves the two half-word vectors (vmrghh/vmrglh) or sums them (vmsumubm).
• No Rc, no XER, no FPSCR. VMX multiply never touches CR, CA, OV, or VSCR.
• No VMX128 sibling. Xbox 360 code that needs this pattern typically goes through vmsumubm instead.

Related Instructions

• vmuloub — odd-lane twin (bytes 1, 3, …, 15).
• vmulesb, vmulosb — signed-byte even/odd multiplies.
• vmuleuh, vmulouh — unsigned-half-word even/odd multiplies (→ word lanes).
• vmulesh, vmulosh — signed-half-word even/odd.
• vmsumubm — fused multiply-sum unsigned-byte-modulo; often replaces the even/odd pair when the caller only needs the sum.
• vmrghh, vmrglh — interleave the even/odd half-word results.

IBM Reference

• AIX 7.3 — vmuleub (Vector Multiply Even Unsigned Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic