xenia-rs/migration/project-root/ppc-manual/vmx/vmulosb.md

vmulosb — Vector Multiply Odd Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000108

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmulosb	vmulosb	—	Vector Multiply Odd Signed Byte

Syntax

vmulosb [VD], [VA], [VB]

Encoding

vmulosb — form VX

• Opcode word: 0x10000108
• Primary opcode (bits 0–5): 4
• Extended opcode: 264
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmulosb: read	Source A vector register.
VB	vmulosb: read	Source B vector register.
VD	vmulosb: write	Destination vector register.

Register Effects

vmulosb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmulosb

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmulosb"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1106
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:109
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:456
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3477-3484

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmulosb => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i8x16(ctx.vr[instr.rb()]);
            let mut r = [0i16; 8];
            for i in 0..8 { r[i] = a[2 * i + 1] as i16 * b[2 * i + 1] as i16; }
            ctx.vr[instr.rd()] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Odd-lane signed-byte multiply. Only the odd-indexed byte lanes (1, 3, 5, 7, 9, 11, 13, 15 — big-endian numbering) of VA and VB participate. Each pair is treated as signed 8-bit, multiplied, and sign-extended to a signed 16-bit result in the corresponding half-word of VD. Pairing: VD.h[i] = (int8)VA.b[2*i+1] * (int8)VB.b[2*i+1] for i ∈ 0..7.
• Lane-count reduction. 16 byte lanes → 8 half-word lanes.
• No overflow. (-128) * (-128) = 0x4000, (127) * (127) = 0x3F01 — both fit in int16. VSCR[SAT] is not set.
• Pair with vmulesb to get every signed byte × byte product; interleave via vmrghh/vmrglh, or feed into vmsummbm for a multiply-accumulate.
• Signed vs. unsigned distinction. The s in vmulosb makes the product arithmetic: negative operands sign-extend. Compare with vmuloub which zero-extends.
• No Rc, no XER, no VSCR side-effect. No VMX128 sibling.

Related Instructions

• vmulesb — even-lane signed byte multiply.
• vmuloub, vmuleub — unsigned byte twins.
• vmulosh, vmulesh — signed half-word even/odd.
• vmsummbm — fused signed-byte multiply-sum modulo.
• vmrghh, vmrglh — interleave the even/odd half-word results.

IBM Reference

• AIX 7.3 — vmulosb (Vector Multiply Odd Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic