xenia-rs/migration/project-root/ppc-manual/fpu/fctidx.md

fctidx — Floating Convert to Integer Doubleword

Category: Floating-Point · Form: X · Opcode: 0xfc00065c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fctid	fctidx	—	Floating Convert to Integer Doubleword
fctid.	fctidx	Rc=1	Floating Convert to Integer Doubleword

Syntax

fctid[Rc] [FD], [FB]

Encoding

fctidx — form X

• Opcode word: 0xfc00065c
• Primary opcode (bits 0–5): 63
• Extended opcode: 814
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fctidx: read	Source B floating-point register.
FD	fctidx: write	Destination floating-point register.
CR	fctidx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fctidx: write	Floating-Point Status and Control Register.

Register Effects

fctidx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fctidx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fctidx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fctidx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:280
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:27
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:912
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2886-2906

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fctidx => {
            // Convert to integer doubleword (round per FPSCR[RN]).
            // PPCBUG-229: set XX on inexact (fractional input).
            let val = ctx.fpr[instr.rb()];
            let result = if val.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXCVI | if fpscr::is_snan(val) { fpscr::VXSNAN } else { 0 });
                0x8000_0000_0000_0000u64
            } else if val >= (i64::MAX as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x7FFF_FFFF_FFFF_FFFFu64
            } else if val < (i64::MIN as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x8000_0000_0000_0000u64
            } else {
                if val != val.trunc() { fpscr::set_exception(ctx, fpscr::XX); }
                fpscr::round_to_i64(ctx, val) as u64
            };
            ctx.fpr[instr.rd()] = f64::from_bits(result);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• binary64 → 64-bit signed integer, current rounding mode. Result is the integer rounded per FPSCR[RN], packed into the 64-bit FPR as raw bits (the FPR is reinterpreted as an i64 by subsequent stfd/integer code).
• Saturation on out-of-range. Per PowerISA, values outside [i64::MIN, i64::MAX] (or NaN) yield the most-negative integer (0x8000_0000_0000_0000) and set FPSCR[VXCVI, VX, FX]. xenia-rs special-cases NaN to 0x8000_0000_0000_0000 but does not saturate out-of-range finite values — Rust's as i64 from a too-large f64 produces an undefined-then-saturated result that may differ from the PPC convention. xenia quirk: very-large finite inputs may round to a different sentinel than hardware.
• xenia round implementation. xenia uses Rust's f64::round, which rounds half-cases away from zero (NOT round-to-nearest-even). PowerISA round-to-nearest in default mode rounds half-cases to even. xenia quirk: values like 0.5, 1.5, 2.5 may produce different integers (xenia: 1, 2, 3; PPC default: 0, 2, 2).
• Rounding mode. PPC uses FPSCR[RN] for the rounding direction. xenia ignores the FPSCR mode and always uses f64::round (i.e. round-half-away-from-zero) regardless of RN. xenia quirk: non-default rounding modes are not respected.
• Inexact. Sets FPSCR[XX, FX] on any non-integer input. xenia does not update FPSCR.
• NaN. Returns sentinel 0x8000_0000_0000_0000 and sets FPSCR[VXCVI]. xenia matches the sentinel, but does not raise the FPSCR bit.
• Rc=1 (fctid.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 814. Reads FRB only.
• Pair with stfd to extract the i64 value to memory or a GPR (Xbox 360 has no direct FPR↔GPR move; round-trip via stack).

Related Instructions

• fctidzx — same conversion but always rounds toward zero (truncation).
• fctiwx, fctiwzx — 32-bit integer variants (saturate to i32 range).
• fcfidx — inverse direction (i64 → binary64).
• mffsx, mtfsfx — control FPSCR[RN].
• stfd, stfiwx — store the integer-bits FPR to memory; stfiwx stores only the low 32 bits (use after fctiwx / fctiwzx).

IBM Reference

• AIX 7.3 — fctid (Floating Convert to Integer Doubleword)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (VXCVI is the invalid-conversion exception bit; saturation sentinel is 0x8000_0000_0000_0000).