e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
144 lines
6.0 KiB
Markdown
144 lines
6.0 KiB
Markdown
# `fdivsx` — Floating Divide Single
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> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xec000024`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `fdivs` | `fdivsx` | — | Floating Divide Single |
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| `fdivs.` | `fdivsx` | Rc=1 | Floating Divide Single |
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## Syntax
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```asm
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fdivs[Rc] [FD], [FA], [FB]
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```
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## Encoding
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### `fdivsx` — form `A`
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- **Opcode word:** `0xec000024`
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- **Primary opcode (bits 0–5):** `59`
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- **Extended opcode:** `18`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (59 or 63) |
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| 6–10 | `FRT` | destination FPR |
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| 11–15 | `FRA` | source A FPR |
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| 16–20 | `FRB` | source B FPR |
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| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
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| 26–30 | `XO` | extended opcode (5 bits) |
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| 31 | `Rc` | record-form flag (updates CR1) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FA` | fdivsx: read | Source A floating-point register (`fr0`–`fr31`). |
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| `FB` | fdivsx: read | Source B floating-point register. |
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| `FD` | fdivsx: write | Destination floating-point register. |
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| `CR` | fdivsx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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| `FPSCR` | fdivsx: write | Floating-Point Status and Control Register. |
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## Register Effects
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### `fdivsx`
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- **Reads (always):** `FA`, `FB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `FPSCR`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `fdivsx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`fdivsx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fdivsx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:71`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L71)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:28`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L28)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:386`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L386)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2627-2637`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2627-L2637)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::fdivsx => {
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let a = ctx.fpr[instr.ra()];
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let b = ctx.fpr[instr.rb()];
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fpscr::check_invalid_div(ctx, a, b);
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fpscr::check_zero_divide(ctx, a, b);
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let result = to_single(ctx, a / b);
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ctx.fpr[instr.rd()] = result;
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fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && b != 0.0);
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if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Single precision.** Result is rounded to IEEE-754 binary32 then re-encoded into the 64-bit FPR. xenia computes `to_single(a / b)`.
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- **Divide by zero.** Finite/±0 sets `FPSCR[ZX, FX]` and yields ±∞. xenia returns the host ±∞ but does not update FPSCR (xenia quirk).
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- **`0 / 0`** → `FPSCR[VXZDZ, VX, FX]`, quiet NaN result.
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- **`±∞ / ±∞`** → `FPSCR[VXIDI, VX, FX]`, quiet NaN result.
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- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX`, plus exception bits `OX`, `UX`, `XX`, `ZX`, `VXZDZ`, `VXIDI`, `VXSNAN`.
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- **`Rc=1` (`fdivs.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
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- **NaN propagation.** Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
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- **Single-precision overflow** returns ±∞ and sets `OX`/`XX`/`FX`.
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- **Performance.** Hardware divide is multi-cycle. Title code commonly uses `fres` + Newton-Raphson for hot loops; this instruction is reserved for non-critical paths.
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- **Denormal flush.** Xenon boots with `FPSCR[NI]=1`; xenia uses host IEEE behavior.
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- **Encoding.** A-form, primary 59, XO 18.
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## Related Instructions
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- [`fdivx`](fdivx.md) — double-precision sibling.
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- [`fresx`](fresx.md) — reciprocal estimate, used to build software divides.
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- [`fmulsx`](fmulsx.md), [`faddsx`](faddsx.md), [`fsubsx`](fsubsx.md) — companion single-precision arithmetic.
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- [`fmaddsx`](fmaddsx.md), [`fnmsubsx`](fnmsubsx.md) — Newton-Raphson refinement helpers.
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- [`frspx`](frspx.md) — explicit double→single rounding.
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## IBM Reference
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- [AIX 7.3 — `fdivs` (Floating Divide Single)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fdivs-floating-divide-single-instruction)
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- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).
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