xenia-rs/migration/project-root/ppc-manual/fpu/fdivsx.md

fdivsx — Floating Divide Single

Category: Floating-Point · Form: A · Opcode: 0xec000024

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fdivs	fdivsx	—	Floating Divide Single
fdivs.	fdivsx	Rc=1	Floating Divide Single

Syntax

fdivs[Rc] [FD], [FA], [FB]

Encoding

fdivsx — form A

• Opcode word: 0xec000024
• Primary opcode (bits 0–5): 59
• Extended opcode: 18
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fdivsx: read	Source A floating-point register (fr0–fr31).
FB	fdivsx: read	Source B floating-point register.
FD	fdivsx: write	Destination floating-point register.
CR	fdivsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fdivsx: write	Floating-Point Status and Control Register.

Register Effects

fdivsx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fdivsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fdivsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fdivsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:71
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:28
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:386
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2627-2637

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fdivsx => {
            let a = ctx.fpr[instr.ra()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_div(ctx, a, b);
            fpscr::check_zero_divide(ctx, a, b);
            let result = to_single(ctx, a / b);
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && b != 0.0);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single precision. Result is rounded to IEEE-754 binary32 then re-encoded into the 64-bit FPR. xenia computes to_single(a / b).
• Divide by zero. Finite/±0 sets FPSCR[ZX, FX] and yields ±∞. xenia returns the host ±∞ but does not update FPSCR (xenia quirk).
• 0 / 0 → FPSCR[VXZDZ, VX, FX], quiet NaN result.
• ±∞ / ±∞ → FPSCR[VXIDI, VX, FX], quiet NaN result.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, plus exception bits OX, UX, XX, ZX, VXZDZ, VXIDI, VXSNAN.
• Rc=1 (fdivs.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow returns ±∞ and sets OX/XX/FX.
• Performance. Hardware divide is multi-cycle. Title code commonly uses fres + Newton-Raphson for hot loops; this instruction is reserved for non-critical paths.
• Denormal flush. Xenon boots with FPSCR[NI]=1; xenia uses host IEEE behavior.
• Encoding. A-form, primary 59, XO 18.

Related Instructions

• fdivx — double-precision sibling.
• fresx — reciprocal estimate, used to build software divides.
• fmulsx, faddsx, fsubsx — companion single-precision arithmetic.
• fmaddsx, fnmsubsx — Newton-Raphson refinement helpers.
• frspx — explicit double→single rounding.

IBM Reference

• AIX 7.3 — fdivs (Floating Divide Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.