xenia-rs/migration/project-root/ppc-manual/fpu/fdivx.md

fdivx — Floating Divide

Category: Floating-Point · Form: A · Opcode: 0xfc000024

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fdiv	fdivx	—	Floating Divide
fdiv.	fdivx	Rc=1	Floating Divide

Syntax

fdiv[Rc] [FD], [FA], [FB]

Encoding

fdivx — form A

• Opcode word: 0xfc000024
• Primary opcode (bits 0–5): 63
• Extended opcode: 18
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fdivx: read	Source A floating-point register (fr0–fr31).
FB	fdivx: read	Source B floating-point register.
FD	fdivx: write	Destination floating-point register.
CR	fdivx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fdivx: write	Floating-Point Status and Control Register.

Register Effects

fdivx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fdivx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- FRA ÷ FRB

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fdivx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fdivx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:55
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:28
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:920
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2616-2626

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fdivx => {
            let a = ctx.fpr[instr.ra()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_div(ctx, a, b);
            fpscr::check_zero_divide(ctx, a, b);
            let result = a / b;
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && b != 0.0);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Double precision. Operates on IEEE-754 binary64; fdivsx is the single-precision sibling.
• Divide by zero. FRA / ±0 (with FRA finite, non-zero) sets FPSCR[ZX, FX] and produces a correctly-signed infinity. xenia relies on host f64 /, which produces the same ±∞ — but does not raise ZX in the interpreter snapshot. xenia quirk: title code that polls FPSCR for divide-by-zero will not observe it.
• 0 / 0 sets FPSCR[VXZDZ, VX, FX] and yields a quiet NaN.
• ±∞ / ±∞ sets FPSCR[VXIDI, VX, FX] and yields a quiet NaN.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits OX, UX, XX, ZX, VXZDZ, VXIDI, VXSNAN. xenia-rs does not maintain these.
• Rc=1 (fdiv.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Performance. Hardware divide is multi-cycle and not pipelined on Xenon. Many titles prefer fres/frsqrte followed by Newton-Raphson refinement (or by fmadd chains) to avoid the divider.
• Denormal flush. Xenon boots with FPSCR[NI]=1; xenia uses host IEEE.
• Encoding. A-form, primary 63, XO 18. FRC is don't-care.

Related Instructions

• fdivsx — single-precision divide.
• fresx — reciprocal estimate ~1/FRB; combined with fmul/fmadd to implement reciprocal divides.
• fmulx, faddx, fsubx — companion arithmetic.
• fmaddx, fnmsubx — used in Newton-Raphson refinement steps.
• mffsx, mtfsfx — FPSCR control (rounding mode, exception masks).

IBM Reference

• AIX 7.3 — fdiv (Floating Divide)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (divide-by-zero and invalid-operation rules).