xenia-rs/migration/project-root/ppc-manual/fpu/fselx.md

fselx — Floating Select

Category: Floating-Point · Form: A · Opcode: 0xfc00002e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsel	fselx	—	Floating Select
fsel.	fselx	Rc=1	Floating Select

Syntax

fsel[Rc] [FD], [FA], [FC], [FB]

Encoding

fselx — form A

• Opcode word: 0xfc00002e
• Primary opcode (bits 0–5): 63
• Extended opcode: 23
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fselx: read	Source A floating-point register (fr0–fr31).
FC	fselx: read	Source C floating-point register (for madd-style ops).
FB	fselx: read	Source B floating-point register.
FD	fselx: write	Destination floating-point register.
CR	fselx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fselx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fselx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fselx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fselx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:144
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:30
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:924
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2774-2783

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fselx => {
            // frD = if frA >= 0.0 then frC else frB
            ctx.fpr[instr.rd()] = if ctx.fpr[instr.ra()] >= 0.0 {
                ctx.fpr[instr.rc()]
            } else {
                ctx.fpr[instr.rb()]
            };
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Non-IEEE branch-free select. PowerPC-specific; not in the IEEE-754 spec. Semantics: FRT = (FRA >= 0.0) ? FRC : FRB. Used pervasively in compiled PPC for min/max/clamp/copysign without branches. xenia-rs uses Rust's >= which matches.
• -0.0 selects FRC. Per PowerISA, -0 compares as >= 0, so it routes to FRC (the "true" branch). xenia's -0.0 >= 0.0 evaluates true in Rust — semantic match.
• NaN selects FRB. Per PowerISA, NaN does not satisfy >= 0, so the result is FRB. xenia: any comparison with NaN returns false in Rust, so >= 0 is false → FRB selected. Match.
• No FPSCR side effects. fsel does not raise VXSNAN even on signalling NaN inputs, and does not update FPRF. It is purely a data-movement op.
• Rc=1 (fsel.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• A-form encoding. Reads FRA, FRB, FRC, writes FRT. Assembler order: fsel FD, FA, FC, FB (note: FRC before FRB).
• Common idioms.
  • min(a,b) = fsel(a-b, b, a)
  • max(a,b) = fsel(a-b, a, b)
  • clamp(x, lo, hi) = fsel(x-lo, fsel(hi-x, x, hi), lo)
  • copysign(x, y) = fsel(y, |x|, -|x|) (using fabs/fnabs)
• Optional ISA. fsel is an optional PowerISA instruction; some implementations trap. Xenon implements it natively.
• No precision change. Bit-pattern selection — no rounding regardless of source precision.

Related Instructions

• fabsx, fnegx, fnabsx — sign-bit ops; common companions for fsel-based copysign/clamp idioms.
• fsubx — subtract is the standard way to produce the comparison key (a - b).
• fcmpux, fcmpox — IEEE compare with branch; the heavyweight alternative to fsel.
• fmrx — unconditional copy.

IBM Reference

• AIX 7.3 — fsel (Floating Select)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (note: fsel is non-IEEE and uses the >= 0 convention, not > 0).