e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
144 lines
6.1 KiB
Markdown
144 lines
6.1 KiB
Markdown
# `fselx` — Floating Select
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> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc00002e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `fsel` | `fselx` | — | Floating Select |
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| `fsel.` | `fselx` | Rc=1 | Floating Select |
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## Syntax
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```asm
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fsel[Rc] [FD], [FA], [FC], [FB]
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```
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## Encoding
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### `fselx` — form `A`
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- **Opcode word:** `0xfc00002e`
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- **Primary opcode (bits 0–5):** `63`
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- **Extended opcode:** `23`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (59 or 63) |
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| 6–10 | `FRT` | destination FPR |
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| 11–15 | `FRA` | source A FPR |
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| 16–20 | `FRB` | source B FPR |
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| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
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| 26–30 | `XO` | extended opcode (5 bits) |
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| 31 | `Rc` | record-form flag (updates CR1) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FA` | fselx: read | Source A floating-point register (`fr0`–`fr31`). |
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| `FC` | fselx: read | Source C floating-point register (for madd-style ops). |
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| `FB` | fselx: read | Source B floating-point register. |
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| `FD` | fselx: write | Destination floating-point register. |
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| `CR` | fselx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `fselx`
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- **Reads (always):** `FA`, `FC`, `FB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `fselx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`fselx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fselx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:144`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L144)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:30`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L30)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:924`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L924)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2774-2783`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2774-L2783)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::fselx => {
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// frD = if frA >= 0.0 then frC else frB
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ctx.fpr[instr.rd()] = if ctx.fpr[instr.ra()] >= 0.0 {
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ctx.fpr[instr.rc()]
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} else {
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ctx.fpr[instr.rb()]
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};
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if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Non-IEEE branch-free select.** PowerPC-specific; not in the IEEE-754 spec. Semantics: `FRT = (FRA >= 0.0) ? FRC : FRB`. Used pervasively in compiled PPC for `min`/`max`/`clamp`/`copysign` without branches. xenia-rs uses Rust's `>=` which matches.
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- **`-0.0` selects `FRC`.** Per PowerISA, `-0` compares as `>= 0`, so it routes to `FRC` (the "true" branch). xenia's `-0.0 >= 0.0` evaluates true in Rust — semantic match.
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- **NaN selects `FRB`.** Per PowerISA, NaN does **not** satisfy `>= 0`, so the result is `FRB`. xenia: any comparison with NaN returns false in Rust, so `>= 0` is false → `FRB` selected. Match.
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- **No FPSCR side effects.** `fsel` does **not** raise `VXSNAN` even on signalling NaN inputs, and does **not** update `FPRF`. It is purely a data-movement op.
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- **`Rc=1` (`fsel.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
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- **A-form encoding.** Reads `FRA, FRB, FRC`, writes `FRT`. Assembler order: `fsel FD, FA, FC, FB` (note: `FRC` before `FRB`).
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- **Common idioms.**
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- `min(a,b) = fsel(a-b, b, a)`
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- `max(a,b) = fsel(a-b, a, b)`
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- `clamp(x, lo, hi) = fsel(x-lo, fsel(hi-x, x, hi), lo)`
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- `copysign(x, y) = fsel(y, |x|, -|x|)` (using `fabs`/`fnabs`)
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- **Optional ISA.** `fsel` is an optional PowerISA instruction; some implementations trap. Xenon implements it natively.
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- **No precision change.** Bit-pattern selection — no rounding regardless of source precision.
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## Related Instructions
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- [`fabsx`](fabsx.md), [`fnegx`](fnegx.md), [`fnabsx`](fnabsx.md) — sign-bit ops; common companions for `fsel`-based copysign/clamp idioms.
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- [`fsubx`](fsubx.md) — subtract is the standard way to produce the comparison key (`a - b`).
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- [`fcmpux`](fcmpu.md), [`fcmpox`](fcmpo.md) — IEEE compare with branch; the heavyweight alternative to `fsel`.
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- [`fmrx`](fmrx.md) — unconditional copy.
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## IBM Reference
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- [AIX 7.3 — `fsel` (Floating Select)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fsel-floating-select-instruction)
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- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (note: `fsel` is non-IEEE and uses the `>= 0` convention, not `> 0`).
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