xenia-rs/migration/project-root/ppc-manual/memory/lvrx.md

lvrx — Load Vector Right Indexed

Category: Memory · Form: X · Opcode: 0x7c00044e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvrx	lvrx	—	Load Vector Right Indexed
lvrx128	lvrx128	—	Load Vector Right Indexed 128

Syntax

lvrx [VD], [RA0], [RB]
lvrx128 [VD], [RA0], [RB]

Encoding

lvrx — form X

• Opcode word: 0x7c00044e
• Primary opcode (bits 0–5): 31
• Extended opcode: 551
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvrx128 — form VX128_1

• Opcode word: 0x10000443
• Primary opcode (bits 0–5): 4
• Extended opcode: 1091
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvrx: read; lvrx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvrx: read; lvrx128: read	Source GPR.
VD	lvrx: write; lvrx128: write	Destination vector register.

Register Effects

lvrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvrx128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:241
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:45
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:822
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3093-3097

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvrx | PpcOpcode::lvrxl => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.rd()] = crate::vmx::load_vector_right(mem, ea);
            ctx.pc += 4;
        }

lvrx128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvrx128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:244
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:45
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:421
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3098-3102

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvrx128 | PpcOpcode::lvrxl128 => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.vd128()] = crate::vmx::load_vector_right(mem, ea);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Load-right half of an unaligned vector. lvrx reads (EA mod 16) bytes at the addresses just below EA & ~0xF (i.e., the bytes from the previous aligned line that fall on the right side of the unaligned vector) and places them in the right (low-address-byte → high-lane) of the destination; the left lanes are zero-filled.
• Standard pair-mate of lvlx. The recipe lvlx VD, RA, RB ; lvrx Vtmp, RA, (RB+16) ; vor VD, VD, Vtmp (or some alignment-aware variant) reconstructs the unaligned 16 bytes spanning the boundary at EA.
• Right vs. left semantics. "Right" refers to lower-numbered (high-significance) lanes after rotation, not in any byte-address sense — see PowerISA Cell BE addenda for the exact bit-position formulas.
• No alignment masking. Like lvlx, the exact EA is used; the value EA mod 16 controls how data is rotated.
• RA0 semantics. RA = 0 selects literal zero.
• Implementation in xenia. The shared snapshot calls vmx::load_vector_right(mem, ea), returning a zero-filled left side and the requested right-bytes payload.
• Microsoft Xbox 360 specific. Part of VMX128 / Cell BE, not in baseline Altivec.
• VMX128 sibling (lvrx128). Identical semantics; alternative operand encoding.
• lvrxl is the LRU-hint variant. Same data; cache hint ignored under emulation.

Related Instructions

• lvlx, lvlx128 — load-left partner.
• lvrxl, lvrxl128 — LRU-hint variants.
• lvx, lvx128 — aligned vector load.
• stvlx, stvrx — symmetric unaligned stores.

IBM Reference

• AIX 7.3 — lvrx (Load Vector Right Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 unaligned-vector idioms.