e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
165 lines
6.9 KiB
Markdown
165 lines
6.9 KiB
Markdown
# `lvx` — Load Vector Indexed
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0000ce`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvx` | `lvx` | — | Load Vector Indexed |
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| `lvx128` | `lvx128` | — | Load Vector Indexed 128 |
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## Syntax
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```asm
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lvx [VD], [RA0], [RB]
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lvx128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvx` — form `X`
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- **Opcode word:** `0x7c0000ce`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `103`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvx128` — form `VX128_1`
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- **Opcode word:** `0x100000c3`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `195`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvx: read; lvx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvx: read; lvx128: read | Source GPR. |
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| `VD` | lvx: write; lvx128: write | Destination vector register. |
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## Register Effects
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### `lvx`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvx128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- ((RA|0) + (RB)) & ~0xF ; align to 16
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VD <- byteswap(MEM(EA, 16))
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```
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## C Translation Example
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```c
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/* lvx VD, RA, RB — 16-byte aligned load of a vector register */
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uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
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uint32_t ea = (uint32_t)((base + r[insn.RB]) & ~(uint64_t)0xF);
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v[insn.VD] = mem_read_vec128_be(ea);
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```
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## Implementation References
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**`lvx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:139`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L139)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:47`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L47)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:775`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L775)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1833-1840`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1833-L1840)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvx => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32; // aligned
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let mut bytes = [0u8; 16];
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for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
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ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(bytes);
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ctx.pc += 4;
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}
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```
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</details>
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**`lvx128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvx128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:142`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L142)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:47`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L47)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:415`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L415)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1841-1848`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1841-L1848)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvx128 => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
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let mut bytes = [0u8; 16];
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for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
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ctx.vr[instr.vd128()] = xenia_types::Vec128::from_bytes(bytes);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Alignment is forced, not checked.** The low four bits of the effective address are **cleared** before the load — passing an unaligned `EA` silently reads from `EA & ~0xF` rather than trapping. This differs from scalar loads (no alignment enforcement) and from `lvewx` etc. (which architecturally use the exact `EA` for lane placement).
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- **Big-endian lane layout.** The byte at the aligned base goes into vector lane 0 (most-significant byte); the byte at base+15 lands in lane 15. On little-endian hosts the 16-byte block is byte-swapped at the memory boundary so the PowerPC-visible layout is preserved.
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- **`RA0` semantics.** When `RA = 0`, the base is the literal zero. Combined with the alignment mask this lets `lvx VD, 0, RB` load from `RB & ~0xF`.
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- **No update form.** Unlike scalar loads, VMX loads have no `u` variant that post-writes the base. Use [`lvxl`](lvxl.md) for the cache-hint variant ("last" — the line is not expected to be reused soon).
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- **VMX128 sibling (`lvx128`).** Identical semantics; the only difference is the operand encoding. VMX128 uses a 7-bit register index split across three non-contiguous bit fields (`VD128l ‖ VD128h`), addressing `v0..v127`.
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- **Atomic 16 bytes.** The read is a single conceptual load; observers see either all 16 old bytes or all 16 new bytes (to the extent the surrounding cache coherency model allows).
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- **Cache-line behaviour.** A 16-byte aligned load fits within one Xenon 128-byte cache line; cold-line cost is one fill.
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## Related Instructions
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- [`stvx`](stvx.md), [`stvx128`](stvx.md) — the store counterparts.
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- [`lvxl`](lvxl.md), [`lvxl128`](lvxl.md) — cache-hint "last-use" load variants.
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- [`lvebx`](lvebx.md), [`lvehx`](lvehx.md), [`lvewx`](lvewx.md) — single-element loads at the exact (sub-aligned) address.
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- [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — load-left / load-right for unaligned vector I/O (combine to read across alignment).
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## IBM Reference
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- [AIX 7.3 — `lvx` (Load Vector Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvx-load-vector-indexed-instruction)
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- `PowerISA v2.07B Book I` "Vector Facility" for full vector-load semantics; `lvx128` is documented in the Xbox 360 XDK.
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