e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
193 lines
7.9 KiB
Markdown
193 lines
7.9 KiB
Markdown
# `stvlxl` — Store Vector Left Indexed LRU
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00070e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `stvlxl` | `stvlxl` | — | Store Vector Left Indexed LRU |
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| `stvlxl128` | `stvlxl128` | — | Store Vector Left Indexed LRU 128 |
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## Syntax
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```asm
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stvlxl [VS], [RA0], [RB]
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stvlxl128 [VS], [RA0], [RB]
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```
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## Encoding
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### `stvlxl` — form `X`
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- **Opcode word:** `0x7c00070e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `903`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `stvlxl128` — form `VX128_1`
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- **Opcode word:** `0x10000703`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1795`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VS` | stvlxl: read; stvlxl128: read | Source vector register (alias for VD on stores). |
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| `RA0` | stvlxl: read; stvlxl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | stvlxl: read; stvlxl128: read | Source GPR. |
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## Register Effects
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### `stvlxl`
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- **Reads (always):** `VS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `stvlxl128`
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- **Reads (always):** `VS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`stvlxl`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvlxl"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:271`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L271)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:77`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L77)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:845`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L845)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3103-3119`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3103-L3119)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::stvlx | PpcOpcode::stvlxl => {
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let ea = ea_indexed(ctx, instr);
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// PPCBUG-513: stvlx/stvlxl were missing invalidate_for_write.
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// store_vector_left writes [ea, (ea & !0xF)+15]; in the worst case (ea & 0xF == 0)
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// that is exactly 16 bytes all within the same 16-byte block, so ea+15 lands in the
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// same 128-byte cache line. Two-call form is kept for defensive correctness.
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() {
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let first_line = ea & !RESERVATION_MASK;
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let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
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t.invalidate_for_write(first_line);
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if last_line != first_line { t.invalidate_for_write(last_line); }
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}
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}
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crate::vmx::store_vector_left(mem, ea, ctx.vr[instr.rs()]);
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ctx.pc += 4;
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}
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```
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</details>
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**`stvlxl128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvlxl128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:274`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L274)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:77`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L77)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:426`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L426)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3120-3133`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3120-L3133)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::stvlx128 | PpcOpcode::stvlxl128 => {
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let ea = ea_indexed(ctx, instr);
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// PPCBUG-513: stvlx128/stvlxl128 were missing invalidate_for_write.
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() {
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let first_line = ea & !RESERVATION_MASK;
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let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
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t.invalidate_for_write(first_line);
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if last_line != first_line { t.invalidate_for_write(last_line); }
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}
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}
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crate::vmx::store_vector_left(mem, ea, ctx.vr[instr.vs128()]);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Same data effect as [`stvlx`](stvlx.md), with LRU cache hint.** Writes `(16 - (EA mod 16))` bytes from the left half of `VS` starting at `EA`; right half not stored. The `l` suffix marks the touched line as least-recently-used.
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- **Hint ignored under emulation.** Xenia's snapshot is shared with `stvlx` (`PpcOpcode::stvlx | PpcOpcode::stvlxl => …`).
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- **No alignment masking.** The exact `EA` controls how data is split.
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- **`RA0` semantics.** `RA = 0` selects literal zero.
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- **Microsoft Xbox 360 specific.** Part of VMX128 / Cell BE.
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- **Streaming write use case.** Pair with [`stvrxl`](stvrxl.md) when the buffer is one-pass output that should not pollute the cache.
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- **VMX128 sibling (`stvlxl128`).** Identical semantics; alternative operand encoding addressing `v0..v127`.
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## Related Instructions
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- [`stvlx`](stvlx.md), [`stvlx128`](stvlx.md) — non-hint variants.
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- [`stvrxl`](stvrxl.md), [`stvrxl128`](stvrxl.md) — store-right LRU partner.
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- [`stvxl`](stvxl.md), [`stvxl128`](stvxl.md) — aligned LRU vector store.
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- [`lvlxl`](lvlxl.md), [`lvrxl`](lvrxl.md) — symmetric LRU loads.
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## IBM Reference
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- [AIX 7.3 — `stvlxl` (Store Vector Left Indexed Last)](https://www.ibm.com/docs/en/aix/7.3.0?topic=reference-instruction-set)
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- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for cache-hint behaviour.
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