xenia-rs/migration/project-root/ppc-manual/vmx/lvsr.md

lvsr — Load Vector for Shift Right Indexed

Category: VMX (Altivec) · Form: X · Opcode: 0x7c00004c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvsr	lvsr	—	Load Vector for Shift Right Indexed
lvsr128	lvsr128	—	Load Vector for Shift Right Indexed 128

Syntax

lvsr [VD], [RA0], [RB]
lvsr128 [VD], [RA0], [RB]

Encoding

lvsr — form X

• Opcode word: 0x7c00004c
• Primary opcode (bits 0–5): 31
• Extended opcode: 38
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvsr128 — form VX128_1

• Opcode word: 0x10000043
• Primary opcode (bits 0–5): 4
• Extended opcode: 67
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvsr: read; lvsr128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvsr: read; lvsr128: read	Source GPR.
VD	lvsr: write; lvsr128: write	Destination vector register.

Register Effects

lvsr

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvsr128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

addr_lo <- ((RA|0) + (RB))[60:63]
for i in 0..15: VD[i] <- 16 − addr_lo + i

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvsr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvsr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:126
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:46
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:762
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2530-2539

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
            let sh = (ea & 0xF) as u8;
            let mut r = [0u8; 16];
            for i in 0..16 { r[i] = (16 - sh) + i as u8; }
            let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
            ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

lvsr128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvsr128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:129
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:46
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:413
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2530-2539

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
            let sh = (ea & 0xF) as u8;
            let mut r = [0u8; 16];
            for i in 0..16 { r[i] = (16 - sh) + i as u8; }
            let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
            ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• No memory access. Like lvsl, lvsr does not touch memory: the effective address is consumed solely to extract the low four bits, which then drive the synthesised permute mask in VD.
• Mirror of lvsl. Where lvsl produces {sh, sh+1, …, sh+15}, lvsr produces {16−sh, 17−sh, …, 31−sh}. When EA & 0xF == 0 the output is {16, 17, …, 31} — the identity permute that selects all of VB (in the vperm VD, VA, VB, VC orientation). When EA & 0xF == 3 the output is {13, 14, …, 28}, splitting the vperm between the high three bytes of VA and the low thirteen of VB.
• Big-endian byte indexing. VD[0] is the most-significant byte (the byte at the lowest address after a stvx).
• Right-shift unaligned-load idiom. Pair with two aligned lvx and a vperm when the source data is laid out so the wanted vector starts in the second aligned block:

  lvx   vAL, r0, rA           ; aligned block at EA & ~0xF
  lvx   vAH, r0, rA + 16      ; next aligned block
  lvsr  vC,  r0, rA           ; right-shift permute mask
  vperm vD,  vAH, vAL, vC     ; note: vAH then vAL — opposite of lvsl
  

  The argument flip versus the lvsl idiom is the whole reason both masks exist.
• RA0 semantics. When RA = 0 the base is the literal zero, so lvsr vD, 0, rB derives the mask from rB & 0xF.
• Selectors >15 are intentional. Inside vperm, byte selectors with bit 4 set (i.e. >= 16) index into the second source vector. lvsr deliberately produces values up to 31, since only the low five bits are honoured by vperm.
• VMX128 sibling (lvsr128). Identical semantics; the extended VD128l ‖ VD128h encoding lets vD reach v0..v127.
• No flags, no exceptions, trivially reorderable.

Related Instructions

• lvsl — the mirror: VD[i] = sh + i.
• vperm — consumes the mask to perform arbitrary byte-level permutation across two vectors.
• lvx, lvlx, lvrx — the actual memory loads that supply the two aligned halves.
• vsldoi — when the misalignment is a compile-time constant, the static-offset shift is cheaper than the lvsr/vperm pair.

IBM Reference

• AIX 7.3 — lvsr (Load Vector for Shift Right Indexed)
• IBM AltiVec Technology Programmer's Interface Manual — unaligned-load idiom