e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
182 lines
7.9 KiB
Markdown
182 lines
7.9 KiB
Markdown
# `lvsr` — Load Vector for Shift Right Indexed
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00004c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvsr` | `lvsr` | — | Load Vector for Shift Right Indexed |
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| `lvsr128` | `lvsr128` | — | Load Vector for Shift Right Indexed 128 |
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## Syntax
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```asm
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lvsr [VD], [RA0], [RB]
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lvsr128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvsr` — form `X`
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- **Opcode word:** `0x7c00004c`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `38`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvsr128` — form `VX128_1`
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- **Opcode word:** `0x10000043`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `67`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvsr: read; lvsr128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvsr: read; lvsr128: read | Source GPR. |
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| `VD` | lvsr: write; lvsr128: write | Destination vector register. |
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## Register Effects
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### `lvsr`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvsr128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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addr_lo <- ((RA|0) + (RB))[60:63]
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for i in 0..15: VD[i] <- 16 − addr_lo + i
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`lvsr`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvsr"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:126`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L126)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:46`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L46)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:762`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L762)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2530-2539`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2530-L2539)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
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let sh = (ea & 0xF) as u8;
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let mut r = [0u8; 16];
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for i in 0..16 { r[i] = (16 - sh) + i as u8; }
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let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
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ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`lvsr128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvsr128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:129`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L129)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:46`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L46)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:413`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L413)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2530-2539`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2530-L2539)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
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let sh = (ea & 0xF) as u8;
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let mut r = [0u8; 16];
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for i in 0..16 { r[i] = (16 - sh) + i as u8; }
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let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
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ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **No memory access.** Like [`lvsl`](lvsl.md), `lvsr` does not touch memory: the effective address is consumed solely to extract the low four bits, which then drive the synthesised permute mask in `VD`.
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- **Mirror of `lvsl`.** Where `lvsl` produces `{sh, sh+1, …, sh+15}`, `lvsr` produces `{16−sh, 17−sh, …, 31−sh}`. When `EA & 0xF == 0` the output is `{16, 17, …, 31}` — the identity permute that selects all of `VB` (in the `vperm VD, VA, VB, VC` orientation). When `EA & 0xF == 3` the output is `{13, 14, …, 28}`, splitting the `vperm` between the high three bytes of `VA` and the low thirteen of `VB`.
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- **Big-endian byte indexing.** `VD[0]` is the most-significant byte (the byte at the lowest address after a `stvx`).
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- **Right-shift unaligned-load idiom.** Pair with two aligned `lvx` and a `vperm` when the source data is laid out so the wanted vector starts in the *second* aligned block:
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```
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lvx vAL, r0, rA ; aligned block at EA & ~0xF
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lvx vAH, r0, rA + 16 ; next aligned block
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lvsr vC, r0, rA ; right-shift permute mask
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vperm vD, vAH, vAL, vC ; note: vAH then vAL — opposite of lvsl
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```
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The argument flip versus the `lvsl` idiom is the whole reason both masks exist.
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- **`RA0` semantics.** When `RA = 0` the base is the literal zero, so `lvsr vD, 0, rB` derives the mask from `rB & 0xF`.
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- **Selectors >15 are intentional.** Inside `vperm`, byte selectors with bit 4 set (i.e. `>= 16`) index into the second source vector. `lvsr` deliberately produces values up to `31`, since only the low five bits are honoured by `vperm`.
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- **VMX128 sibling (`lvsr128`).** Identical semantics; the extended `VD128l ‖ VD128h` encoding lets `vD` reach `v0..v127`.
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- **No flags, no exceptions, trivially reorderable.**
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## Related Instructions
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- [`lvsl`](lvsl.md) — the mirror: `VD[i] = sh + i`.
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- [`vperm`](vperm.md) — consumes the mask to perform arbitrary byte-level permutation across two vectors.
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- [`lvx`](lvx.md), [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — the actual memory loads that supply the two aligned halves.
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- [`vsldoi`](vsldoi.md) — when the misalignment is a compile-time constant, the static-offset shift is cheaper than the `lvsr`/`vperm` pair.
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## IBM Reference
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- [AIX 7.3 — `lvsr` (Load Vector for Shift Right Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvsr-load-vector-shift-right-indexed-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual — unaligned-load idiom](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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