xenia-rs/migration/project-root/ppc-manual/vmx/vadduws.md

vadduws — Vector Add Unsigned Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000280

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduws	vadduws	—	Vector Add Unsigned Word Saturate

Syntax

vadduws [VD], [VA], [VB]

Encoding

vadduws — form VX

• Opcode word: 0x10000280
• Primary opcode (bits 0–5): 4
• Extended opcode: 640
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduws: read	Source A vector register.
VB	vadduws: read	Source B vector register.
VD	vadduws: write	Destination vector register.
VSCR	vadduws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vadduws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vadduws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduws

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vadduws"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:409
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:90
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:489
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3330-3341

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vadduws => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::sat_add_u32(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Four unsigned-word lanes, saturating. Each VD[i] = min(VA[i] + VB[i], 0xFFFF_FFFF) for i = 0..3. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• VSCR[SAT] is sticky-set if any lane clamps. Cleared only via mtvscr. Xenia uses crate::vmx::sat_add_u32 (crates/xenia-cpu/src/vmx.rs).
• One-sided clamp at UINT32_MAX. There is no underflow path for unsigned add.
• The modulo counterpart is vadduwm. Use vadduws only when overflow needs to be visible / clamped; otherwise the modulo form is one cycle and never touches the sticky bit.
• No XER side effects, no carry exposure. Unlike vadduwm + vaddcuw, the saturating form does not make the carry available — it is fused into the clamp.
• No VMX128 sibling.
• Common usage. Pixel sums where four packed unsigned 32-bit accumulators must clip at white; counter overflow detection.

Related Instructions

• vadduwm — same width, modulo add (no saturation, no SAT flag).
• vaddsws — same width, signed saturating add.
• vaddubs, vadduhs — unsigned saturating add at byte / half width.
• vsubuws — the matching unsigned saturating subtract.
• vaddcuw — explicit carry-out (paired with the modulo form).
• mtvscr / mfvscr — read or clear the sticky VSCR[SAT] bit.

IBM Reference

• AIX 7.3 — vadduws (Vector Add Unsigned Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic