xenia-rs/migration/project-root/ppc-manual/vmx/vcmpequw.md

vcmpequw — Vector Compare Equal-to Unsigned Word

Category: VMX (Altivec) · Form: VC · Opcode: 0x10000086

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpequw	vcmpequw	—	Vector Compare Equal-to Unsigned Word
vcmpequw.	vcmpequw	Rc=1	Vector Compare Equal-to Unsigned Word
vcmpequw128	vcmpequw128	—	Vector128 Compare Equal-to Unsigned Word
vcmpequw128.	vcmpequw128	Rc=1	Vector128 Compare Equal-to Unsigned Word

Syntax

vcmpequw[Rc] [VD], [VA], [VB]
vcmpequw128[Rc] [VD], [VA], [VB]

Encoding

vcmpequw — form VC

• Opcode word: 0x10000086
• Primary opcode (bits 0–5): 4
• Extended opcode: 134
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

vcmpequw128 — form VX128_R

• Opcode word: 0x18000200
• Primary opcode (bits 0–5): 6
• Extended opcode: 512
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22–25	XO	extended opcode (compare)
26	VA128h	source A middle bit
27	Rc	record-form flag (updates CR6)
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vcmpequw: read; vcmpequw128: read	Source A vector register.
VB	vcmpequw: read; vcmpequw128: read	Source B vector register.
VD	vcmpequw: write; vcmpequw128: write	Destination vector register.
CR	vcmpequw: write (conditional); vcmpequw128: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpequw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

vcmpequw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpequw: CR6 ← [all-true, 0, all-false, 0] when Rc=1.
• vcmpequw128: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpequw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcmpequw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:727
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:95
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:559
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2542-2552

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcmpequw | PpcOpcode::vcmpequw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = if a[i] == b[i] { 0xFFFF_FFFF } else { 0 }; }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            let rc = if matches!(instr.opcode, PpcOpcode::vcmpequw128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
            if rc { update_cr6_from_vmask(&r, ctx); }
            ctx.pc += 4;
        }

vcmpequw128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcmpequw128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:731
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:95
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:685
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2542-2552

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcmpequw | PpcOpcode::vcmpequw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = if a[i] == b[i] { 0xFFFF_FFFF } else { 0 }; }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            let rc = if matches!(instr.opcode, PpcOpcode::vcmpequw128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
            if rc { update_cr6_from_vmask(&r, ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-word mask: all-ones / all-zero. Four word lanes; VD[i] = (VA[i] == VB[i]) ? 0xFFFFFFFF : 0. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Sign-agnostic. Equality is bit-identical for signed and unsigned words; there is no vcmpeqsw.
• CR6 update when Rc=1 (vcmpequw.). CR6 = [lt = all-true, gt = 0, eq = all-false, so = 0]. Classic "did all four 32-bit hash buckets match?" early-out pattern.
• Compose with vsel. Mask drives vsel per word.
• Common usage. Hashtable probe matching, packed-RGBA pixel comparisons, packed-int handle equality.
• No VSCR interaction, no XER, no traps.
• Aliasing legal.
• VMX128 sibling (vcmpequw128). Identical semantics with the extended encoding; xenia routes both to one match arm via vmx_reg_triple.

Related Instructions

• vcmpequb, vcmpequh — equality compare at byte / half width.
• vcmpgtuw, vcmpgtsw — > at word width, unsigned / signed.
• vcmpeqfp — same shape, IEEE-754 single-precision equality.
• vsel, vand, vandc, vor, vxor — mask consumers / combinators.
• vspltisw, vspltw — broadcast sources for needle patterns.

IBM Reference

• AIX 7.3 — vcmpequw (Vector Compare Equal-to Unsigned Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares