xenia-rs/migration/project-root/ppc-manual/vmx/vsum2sws.md

vsum2sws — Vector Sum Across Partial (1/2) Signed Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000688

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsum2sws	vsum2sws	—	Vector Sum Across Partial (1/2) Signed Word Saturate

Syntax

vsum2sws [VD], [VA], [VB]

Encoding

vsum2sws — form VX

• Opcode word: 0x10000688
• Primary opcode (bits 0–5): 4
• Extended opcode: 1672
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsum2sws: read	Source A vector register.
VB	vsum2sws: read	Source B vector register.
VD	vsum2sws: write	Destination vector register.
VSCR	vsum2sws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vsum2sws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vsum2sws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsum2sws

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsum2sws"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1776
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:127
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:545
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3668-3679

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsum2sws => {
            // Two 2-word partial sums at lanes 1 and 3.
            let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let s0 = a[0] as i64 + a[1] as i64 + c[1] as i64;
            let s1 = a[2] as i64 + a[3] as i64 + c[3] as i64;
            let (v0, sat0) = crate::vmx::sat_i64_to_i32(s0);
            let (v1, sat1) = crate::vmx::sat_i64_to_i32(s1);
            if sat0 | sat1 { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4([0, v0, 0, v1]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Two 2-word partial sums. The four signed-word lanes of VA are split into two pairs: {VA.w[0], VA.w[1]} and {VA.w[2], VA.w[3]}. Each pair is summed, then added to the matching "anchor" word of VB (VB.w[1] and VB.w[3] respectively). Each 33-bit intermediate result is saturated to int32.
• Output lane placement. VD.w[0] = 0, VD.w[1] = sat(VA.w[0] + VA.w[1] + VB.w[1]), VD.w[2] = 0, VD.w[3] = sat(VA.w[2] + VA.w[3] + VB.w[3]). The zero lanes are specified in the ISA — software that wants a contiguous pair must vmrglw / vmrghw afterwards.
• Sticky VSCR[SAT] set when either saturating truncation occurs.
• Big-endian word lanes.
• No Rc, no XER.
• No VMX128 sibling.

Related Instructions

• vsumsws — full 4-lane sum.
• vsum4sbs, vsum4shs, vsum4ubs — per-word partial sums at narrower input widths.
• vaddsws, vsubsws — word-saturating arithmetic.

IBM Reference

• AIX 7.3 — vsum2sws (Vector Sum across Partial (1/2) Saturated Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic