xenia-rs/migration/project-root/ppc-manual/vmx/vsumsws.md

vsumsws — Vector Sum Across Signed Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000788

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsumsws	vsumsws	—	Vector Sum Across Signed Word Saturate

Syntax

vsumsws [VD], [VA], [VB]

Encoding

vsumsws — form VX

• Opcode word: 0x10000788
• Primary opcode (bits 0–5): 4
• Extended opcode: 1928
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsumsws: read	Source A vector register.
VB	vsumsws: read	Source B vector register.
VD	vsumsws: write	Destination vector register.
VSCR	vsumsws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vsumsws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vsumsws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsumsws

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsumsws"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1771
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:127
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:550
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3658-3667

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsumsws => {
            // vD[3] = sat_i32(vC[3] + sum over i in 0..4 of vA[i])
            let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let s = a.iter().map(|&x| x as i64).sum::<i64>() + c[3] as i64;
            let (v, sat) = crate::vmx::sat_i64_to_i32(s);
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4([0, 0, 0, v]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Full 4-lane reduction (signed word). Sum all four signed words of VA plus VB.w[3]; saturate to int32. Output: VD.w[3] = sat(VA.w[0]+VA.w[1]+VA.w[2]+VA.w[3]+VB.w[3]); VD.w[0..2] = 0.
• Only the last lane is meaningful. The specification writes zeros into the first three lanes so software cannot accidentally consume them.
• Sticky VSCR[SAT] set on overflow.
• Equivalent to a horizontal add-reduce, common terminator for a multi-step dot-product or sum-of-products pipeline.
• Big-endian word lanes.
• No Rc, no XER.
• No VMX128 sibling. VMX128 instead uses vmsum3fp128 / vmsum4fp128 for float dot-products.

Related Instructions

• vsum2sws — two 2-word partial sums.
• vsum4sbs, vsum4shs, vsum4ubs — per-word partial sums at narrower input widths.
• vmsumshm, vmsumshs — fused multiply-sum variants.
• vmsum3fp128, vmsum4fp128 — VMX128 float dot-product helpers.

IBM Reference

• AIX 7.3 — vsumsws (Vector Sum across Saturated Signed Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic