Sylpheed/tools/ppc-manual/alu/andix.md

andi. — AND Immediate

Category: Integer ALU · Form: D · Opcode: 0x70000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
andi.	andi.	—	AND Immediate

Syntax

andi. [RA], [RS], [UIMM]

Encoding

andi. — form D

• Opcode word: 0x70000000
• Primary opcode (bits 0–5): 28
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	andi.: read	Source GPR (alias for RD in some stores).
UIMM	andi.: read	16-bit unsigned immediate. Zero-extended.
RA	andi.: write	Source GPR (r0–r31).
CR	andi.: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andi.

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA, CR
• Writes (conditional): none

Status-Register Effects

• andi.: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andi.

• Canary XML: tools/ppc-instructions.xml — search for mnem="andi."
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:657
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:19
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:466

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_andix(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) & (i48.0 || UI)
  Value* ra = f.And(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS)));
  f.StoreGPR(i.D.RA, ra);
  f.UpdateCR(0, ra);
  return 0;
}

Special Cases & Edge Conditions

• Always Rc=1. There is no andi (without the dot). The mnemonic is andi. and the encoding always updates CR0. If you need a non-record AND-with-immediate, you have to materialise the immediate first (e.g. with li/lis) and use andx.
• Immediate is zero-extended. The 16-bit UIMM is widened with zeros, so andi. rA, rS, 0xFFFF masks rS to its low 16 bits — the high 48 bits of the 64-bit register are forced to zero.
• Cannot mask the high half of a register in one instruction. The immediate covers bits 48–63 only; for higher bits use andisx (covers bits 32–47) or compose with rlwinm/rldicl.
• CR0 update is unconditional. This is part of the encoding, not a flag — the primary opcode (28) is andi..
• Common idiom: andi. r0, rN, mask to test bits without disturbing the source — but note r0 is overwritten and CR0 is set. If you only need the CR result, prefer extrwi/rlwinm. for arbitrary masks.
• 64-bit CR update on Xenon, 32-bit in Canary. Since the AND result has zeros in bits 0–47, Canary's INT32 truncation is harmless here — the result fits in 16 bits, so spec and Canary agree.

Related Instructions

• andisx — same op with immediate shifted left 16 (covers bits 32–47).
• andx, andcx — register AND family.
• ori, oris, xori, xoris — sister immediate logicals (notably without a record form).
• rlwinmx — for masks that don't fit into a 16-bit immediate.

IBM Reference

• AIX 7.3 — andi. (AND Immediate)