Sylpheed/tools/ppc-manual/alu/orcx.md

orcx — OR with Complement

Category: Integer ALU · Form: X · Opcode: 0x7c000338

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
orc	orcx	—	OR with Complement
orc.	orcx	Rc=1	OR with Complement

Syntax

orc[Rc] [RA], [RS], [RB]

Encoding

orcx — form X

• Opcode word: 0x7c000338
• Primary opcode (bits 0–5): 31
• Extended opcode: 412
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	orcx: read	Source GPR (alias for RD in some stores).
RB	orcx: read	Source GPR.
RA	orcx: write	Source GPR (r0–r31).
CR	orcx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

orcx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• orcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) | ~(RB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

orcx

• Canary XML: tools/ppc-instructions.xml — search for mnem="orcx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:800
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:199
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:922

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_orcx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) | ¬(RB)
  Value* ra = f.Or(f.LoadGPR(i.X.RT), f.Not(f.LoadGPR(i.X.RB)));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← RS OR (NOT RB). The complement is on RB. Useful for setting bits outside a mask — e.g. orc r3, r3, r4 sets in r3 every bit not set in r4.
• Idiom: orc RA, RS, RS = RS | ~RS = -1 (all ones). Cheaper-looking than constructing −1 via lis+ori, but the assembler usually prefers li RA, -1 or eqv RA, RS, RS.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; Canary emits a full-width f.Or(RS, f.Not(RB)).
• No OE or XER side effects.
• Rc=1 CR0 update truncates to 32 bits in Canary (f.UpdateCR(0, v)). Because ~RB typically has high bits set, orc. results whose low word's sign differs from the full word's give different CR0 in spec and Canary.

Related Instructions

• orx — base OR (no complement).
• andcx — AND-with-complement; sister c form.
• norx, nandx — full-result complements.
• eqvx — ~(RS XOR RB).

IBM Reference

• AIX 7.3 — orc (OR with Complement)