Sylpheed/tools/ppc-manual/alu/eqvx.md

eqvx — Equivalent

Category: Integer ALU · Form: X · Opcode: 0x7c000238

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
eqv	eqvx	—	Equivalent
eqv.	eqvx	Rc=1	Equivalent

Syntax

eqv[Rc] [RA], [RS], [RB]

Encoding

eqvx — form X

• Opcode word: 0x7c000238
• Primary opcode (bits 0–5): 31
• Extended opcode: 284
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	eqvx: read	Source GPR (alias for RD in some stores).
RB	eqvx: read	Source GPR.
RA	eqvx: write	Source GPR (r0–r31).
CR	eqvx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

eqvx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• eqvx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) ^ (RB))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

eqvx

• Canary XML: tools/ppc-instructions.xml — search for mnem="eqvx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:704
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:59
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:911

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_eqvx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) == (RB)
  Value* ra = f.Not(f.Xor(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• NXOR / equivalence. RA ← ~(RS XOR RB). A bit in RA is 1 iff the corresponding bits of RS and RB are equal. Useful as a per-bit equality test feeding into a cntlzw for run-length analysis.
• Idiom: eqv RA, RS, RS sets every bit to 1 — a one-instruction RA = -1. Cheaper than li RA, -1 followed by oris/ori for full 64-bit -1.
• Operand convention is X-form (RA is destination; RS, RB are sources).
• 64-bit operation on Xenon; ~ is full 64-bit on u64.
• No OE, no XER side effects. Only Rc=1 updates CR0.
• 64-bit CR update on Xenon, 32-bit in Canary. f.UpdateCR(0, v) compares only the low 32 bits, so spec and Canary disagree whenever the high word decides the sign, or the low word is zero while the high word is not.

Related Instructions

• xorx — base XOR (eqv is xor then not).
• andx, orx, nandx, norx, andcx, orcx — full logical family.
• xori, xoris — immediate XOR (no immediate eqv exists).

IBM Reference

• AIX 7.3 — eqv (Equivalent)