Sylpheed/tools/ppc-manual/alu/andcx.md

andcx — AND with Complement

Category: Integer ALU · Form: X · Opcode: 0x7c000078

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
andc	andcx	—	AND with Complement
andc.	andcx	Rc=1	AND with Complement

Syntax

andc[Rc] [RA], [RS], [RB]

Encoding

andcx — form X

• Opcode word: 0x7c000078
• Primary opcode (bits 0–5): 31
• Extended opcode: 60
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	andcx: read	Source GPR (alias for RD in some stores).
RB	andcx: read	Source GPR.
RA	andcx: write	Source GPR (r0–r31).
CR	andcx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andcx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• andcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) & ~(RB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andcx

• Canary XML: tools/ppc-instructions.xml — search for mnem="andcx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:647
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:17
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:883

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_andcx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) & ¬(RB)
  Value* ra = f.AndNot(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• andc RA, RS, RB computes RS AND (NOT RB). The complement is applied to RB, not RS. Useful for clearing a bitmask: andc r3, r3, r4 clears in r3 every bit set in r4.
• Common idiom: andc r3, r3, r3 zeroes r3 (every bit ANDed with its own complement). Cheaper-looking than xor r3, r3, r3 on some pipelines but functionally identical; the assembler often prefers the xor idiom.
• Operand convention is the X-form one (RA is the destination, RS and RB are sources). Same gotcha as andx.
• No OE/XER side effects. Only CR0 is updated when Rc=1.
• 64-bit operation on Xenon; the AND is computed across all 64 bits of RS and ~RB. Canary emits a single full-width f.AndNot(RS, RB).
• 64-bit CR update on Xenon, 32-bit in Canary — f.UpdateCR(0, ra), the same INT32 truncation.

Related Instructions

• andx — plain AND (no complement).
• nandx — NAND (~(RS & RB)).
• orcx — OR with complement; sister c form.
• eqvx — ~(RS ^ RB) (NXOR / equivalence).
• norx — NOR.

IBM Reference

• AIX 7.3 — andc (AND with Complement)