Sylpheed/tools/ppc-manual/alu/norx.md

norx — NOR

Category: Integer ALU · Form: X · Opcode: 0x7c0000f8

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
nor	norx	—	NOR
nor.	norx	Rc=1	NOR

Syntax

nor[Rc] [RA], [RS], [RB]

Encoding

norx — form X

• Opcode word: 0x7c0000f8
• Primary opcode (bits 0–5): 31
• Extended opcode: 124
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	norx: read	Source GPR (alias for RD in some stores).
RB	norx: read	Source GPR.
RA	norx: write	Source GPR (r0–r31).
CR	norx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

norx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• norx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) | (RB))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

norx

• Canary XML: tools/ppc-instructions.xml — search for mnem="norx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:763
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:198
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:892

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_norx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- ¬((RS) | (RB))
  Value* ra = f.Not(f.Or(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ~(RS OR RB). Bit-wise NOR. The canonical idiom for one-instruction NOT: not RA, RS is the simplified mnemonic for nor RA, RS, RS — both source operands the same yields ~RS. Almost every disassembly contains this pattern.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; full 64-bit complement via ! on u64.
• No OE or XER side effects.
• Rc=1 CR0 update truncates to 32 bits in Canary (f.UpdateCR(0, v)). NOR almost always sets high bits; the low word's sign decides Canary's CR0, the full word's sign decides spec's.
• nor. after a clear-low operation is a common pattern for testing whether some high-bit mask is empty.

Related Instructions

• orx, orcx — base OR family.
• andx, andcx, nandx — AND family.
• eqvx — NXOR.
• xorx — XOR.
• not (simplified mnemonic for nor RA, RS, RS).

IBM Reference

• AIX 7.3 — nor (NOR)
• AIX 7.3 — not (simplified mnemonic)