Sylpheed/tools/ppc-manual/control/creqv.md

creqv — Condition Register Equivalent

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000242

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
creqv	creqv	—	Condition Register Equivalent

Syntax

creqv [CRBD], [CRBA], [CRBB]

Encoding

creqv — form XL

• Opcode word: 0x4c000242
• Primary opcode (bits 0–5): 19
• Extended opcode: 289
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	creqv: read	CR source bit A (0–31).
CRBB	creqv: read	CR source bit B (0–31).
CRBD	creqv: write	CR destination bit (0–31).

Register Effects

creqv

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

creqv

• Canary XML: tools/ppc-instructions.xml — search for mnem="creqv"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:370
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:37
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:833

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_creqv(PPCHIRBuilder& f, const InstrData& i) {
  // CR[bt] <- CR[ba] == CR[bb]   bt=bo, ba=bi, bb=bb
  Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
  Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
  Value* bt = f.CompareEQ(ba, bb);
  f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
  return 0;
}

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← ¬(CR[CRBA] XOR CR[CRBB]) — i.e. logical equivalence (XNOR). Result is 1 iff CRBA and CRBB agree.
• crset BT idiom. With identical operands, creqv BT, BT, BT always yields 1 (any bit XNOR'd with itself is 1). This is the canonical PowerPC set-to-1 for a single CR bit; assemblers recognise the simplified mnemonic crset BT.
• Bit-level operands. Like all CR-logical ops, the three operands are 5-bit absolute CR-bit indices (0..31). Mixing CR fields is fine.
• Use case. Branch on "A == B" of two prior compare results. Example: crxor of CR0.SO and CR1.SO gives "differ"; creqv gives "agree".
• No Rc / OE. Doesn't touch CR0, XER, or any other state beyond the named bit.
• Not synchronising. Reorderable.
• Canary status. Canary emits the host equality compare of the two bits (XNOR). The crset simplified form is the most common occurrence in real Xbox 360 code.

Related Instructions

• crand, crandc — AND family.
• cror, crorc, crnor, crnand — OR family.
• crxor — the dual; crxor BT, BT, BT is the standard clear-to-0 idiom.
• mcrf — bulk CR-field move.
• bcx — consumes the synthesised bit.

Simplified Mnemonics

Simplified	Expansion	Effect
crset BT	creqv BT, BT, BT	force CR[BT] ← 1

IBM Reference

• AIX 7.3 — creqv (Condition Register Equivalent)
• AIX 7.3 — Condition register simplified mnemonics