Sylpheed/tools/ppc-manual/control/crnand.md

crnand — Condition Register NAND

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c0001c2

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
crnand	crnand	—	Condition Register NAND

Syntax

crnand [CRBD], [CRBA], [CRBB]

Encoding

crnand — form XL

• Opcode word: 0x4c0001c2
• Primary opcode (bits 0–5): 19
• Extended opcode: 225
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	crnand: read	CR source bit A (0–31).
CRBB	crnand: read	CR source bit B (0–31).
CRBD	crnand: write	CR destination bit (0–31).

Register Effects

crnand

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

crnand

• Canary XML: tools/ppc-instructions.xml — search for mnem="crnand"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:379
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:38
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:831

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_crnand(PPCHIRBuilder& f, const InstrData& i) {
  // CR[bt] <- ¬(CR[ba] & CR[bb])   bt=bo, ba=bi, bb=bb
  Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
  Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
  Value* bt = f.And(f.Not(f.And(ba, bb)), f.LoadConstantInt8(0x01));
  f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
  return 0;
}

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← ¬(CR[CRBA] AND CR[CRBB]). Result is 0 only when both source bits are 1; otherwise 1.
• Bit-level operands. 5-bit absolute CR-bit indices, identical to the rest of the CR-logical family. Source and destination bits may all be in different CR fields.
• Identity case. crnand BT, BA, BA ≡ ¬CR[BA] — a one-instruction CR-bit invert. Less common than crxor against a crset-prepared 1-bit, but legal.
• Use case. Branch on "NOT (A AND B)". Less common than the De Morgan equivalent (cror BT, ¬A, ¬B), but saves an extra crnot step.
• No Rc / OE. No CR0 / XER side effects.
• Not synchronising. Reorderable.
• Canary status. Canary's InstrEmit_crnand emits a host AND followed by NOT.

Related Instructions

• crand, crandc — non-negated AND siblings.
• crnor — negated OR (the De Morgan dual).
• cror, crorc — OR family.
• crxor, creqv — XOR / XNOR.
• mcrf — copy a 4-bit CR field wholesale.
• bcx — typical consumer.

crnand has no dedicated simplified mnemonic. Use crand + a separate complement, or use crnand BT, BA, BA to invert a single bit.

IBM Reference

• AIX 7.3 — crnand (Condition Register NAND)
• AIX 7.3 — Condition register simplified mnemonics