Sylpheed/tools/ppc-manual/control/crnor.md

crnor — Condition Register NOR

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000042

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
crnor	crnor	—	Condition Register NOR

Syntax

crnor [CRBD], [CRBA], [CRBB]

Encoding

crnor — form XL

• Opcode word: 0x4c000042
• Primary opcode (bits 0–5): 19
• Extended opcode: 33
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	crnor: read	CR source bit A (0–31).
CRBB	crnor: read	CR source bit B (0–31).
CRBD	crnor: write	CR destination bit (0–31).

Register Effects

crnor

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

crnor

• Canary XML: tools/ppc-instructions.xml — search for mnem="crnor"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:388
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:39
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:827

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_crnor(PPCHIRBuilder& f, const InstrData& i) {
  // CR[bt] <- ¬(CR[ba] | CR[bb])   bt=bo, ba=bi, bb=bb
  Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
  Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
  Value* bt = f.And(f.Not(f.Or(ba, bb)), f.LoadConstantInt8(0x01));
  f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
  return 0;
}

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← ¬(CR[CRBA] OR CR[CRBB]). Result is 1 only when both source bits are 0; otherwise 0.
• crnot BT, BA idiom. With BA == BB, crnor BT, BA, BA ≡ ¬CR[BA] — this is the canonical PowerPC single-bit invert, recognised by assemblers as the simplified mnemonic crnot BT, BA.
• Bit-level operands. 5-bit absolute CR-bit indices (0..31). The three bits may live in any combination of the eight CR fields.
• Use case. Branch on "neither A nor B"; or, with crnot, simply complement a CR bit before consuming it in a bcx.
• No Rc / OE. Pure CR-bit dataflow; CR0/XER untouched.
• Not synchronising. Reorderable.
• Canary status. Canary's InstrEmit_crnor emits a host OR followed by NOT.

Related Instructions

• cror, crorc — non-negated OR siblings.
• crnand — negated AND (the De Morgan dual).
• crand, crandc — AND family.
• crxor, creqv — XOR / XNOR.
• mcrf — bulk CR-field copy.
• bcx — typical consumer of synthesised CR bits.

Simplified Mnemonics

Simplified	Expansion	Effect
crnot BT, BA	crnor BT, BA, BA	CR[BT] ← ¬CR[BA] (invert single bit)

IBM Reference

• AIX 7.3 — crnor (Condition Register NOR)
• AIX 7.3 — Condition register simplified mnemonics