Sylpheed/tools/ppc-manual/fpu/faddsx.md

faddsx — Floating Add Single

Category: Floating-Point · Form: A · Opcode: 0xec00002a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fadds	faddsx	—	Floating Add Single
fadds.	faddsx	Rc=1	Floating Add Single

Syntax

fadds[Rc] [FD], [FA], [FB]

Encoding

faddsx — form A

• Opcode word: 0xec00002a
• Primary opcode (bits 0–5): 59
• Extended opcode: 21
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	faddsx: read	Source A floating-point register (fr0–fr31).
FB	faddsx: read	Source B floating-point register.
FD	faddsx: write	Destination floating-point register.
CR	faddsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	faddsx: write	Floating-Point Status and Control Register.

Register Effects

faddsx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• faddsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- RoundToSingle(FRA + FRB)          ; single-precision

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

faddsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="faddsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:46
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:65
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:503

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_faddsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frA) + (frB)
  Value* v = f.Add(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  v = f.ToSingle(v);
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Single precision via double FPRs. The trailing s in the mnemonic means the result is rounded to IEEE-754 binary32 after the addition, then re-encoded into the 64-bit FPR using the binary64 representation of that single-precision value. The host computes to_single(a + b); both source operands are read as full binary64.
• FPSCR side effects. Hardware updates FPRF (result class), FR/FI (rounding info), FX, and the exception bits — OX on overflow, UX on underflow, XX on inexact, VXISI on ±∞ − ±∞, VXSNAN on a signalling-NaN input. Canary does not compute them: its UpdateFPSCR is a stub that clears FEX and VX, leaves every other FPSCR bit unchanged and, with Rc=1, writes CR1 as all zeros. Don't depend on cross-instruction FPSCR observation when matching Canary.
• Rc=1 (fadds.) copies FPSCR[FX, FEX, VX, OX] into CR1 on hardware. Canary's UpdateFPSCR stub instead writes CR1 as all zeros.
• NaN propagation. Any NaN input yields a quiet NaN result; signalling NaNs are quietened (signalling bit cleared) per PowerISA. Host-native f64 + may not perform that quietening on every platform.
• ±∞ − ±∞ after rounding. Although +-shaped, opposite-signed infinities still produce QNaN(VXISI).
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.
• Rounding mode uses FPSCR[RN] (00 nearest-even, 01 toward 0, 10 toward +∞, 11 toward −∞). Default is nearest-even and is rarely changed.
• A-form encoding ignores FRC. Bits 21–25 are don't-care for the add family.

Related Instructions

• faddx — double-precision sibling.
• fsubsx, fmulsx, fdivsx — other single-precision arithmetic ops.
• fmaddsx, fmsubsx, fnmaddsx, fnmsubsx — fused multiply-add single-precision family (single rounding step).
• frspx — explicit double→single rounding helper; fadds is essentially frsp(fadd) fused into one rounding.
• mffsx, mtfsfx — read/write FPSCR for rounding-mode and exception control.

IBM Reference

• AIX 7.3 — fadds (Floating Add Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (single-precision rounding rules and FPSCR side effects).