Sylpheed/tools/ppc-manual/fpu/fsubsx.md

fsubsx — Floating Subtract Single

Category: Floating-Point · Form: A · Opcode: 0xec000028

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsubs	fsubsx	—	Floating Subtract Single
fsubs.	fsubsx	Rc=1	Floating Subtract Single

Syntax

fsubs[Rc] [FD], [FA], [FB]

Encoding

fsubsx — form A

• Opcode word: 0xec000028
• Primary opcode (bits 0–5): 59
• Extended opcode: 20
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fsubsx: read	Source A floating-point register (fr0–fr31).
FB	fsubsx: read	Source B floating-point register.
FD	fsubsx: write	Destination floating-point register.
CR	fsubsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fsubsx: write	Floating-Point Status and Control Register.

Register Effects

fsubsx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fsubsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fsubsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fsubsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:135
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:95
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:502

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fsubsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frA) - (frB)
  Value* v = f.Sub(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  v = f.ToSingle(v);
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Single precision. Result is rounded to IEEE-754 binary32 then re-encoded into the destination 64-bit FPR using the binary64 representation. Canary emits ToSingle(Sub(a, b)): vsubsd, then the vcvtsd2ss + vcvtss2sd round trip.
• ±∞ − ±∞ sets FPSCR[VXISI, VX, FX] and yields a quiet NaN.
• FPSCR side effects. Always updated on hardware: FPRF, FR, FI, FX, plus exception bits OX, UX, XX, VXISI, VXSNAN. Canary does not maintain FPSCR (UpdateFPSCR is a stub).
• Rc=1 (fsubs.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow. A double-precision result that would round to a binary32 overflow returns ±∞ and sets OX/XX/FX.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.
• Rounding mode is taken from FPSCR[RN]; default is nearest-even.
• Encoding. A-form, primary 59, XO 20. FRC is don't-care.

Related Instructions

• fsubx — double-precision sibling.
• faddsx, fmulsx, fdivsx — companion single-precision ops.
• fmsubsx, fnmsubsx — fused single-precision multiply-subtract.
• fnegx — sign flip used to express subtract as add-of-negation.
• frspx — explicit double→single rounding (semantically equivalent to chaining frsp(fsub(...))).

IBM Reference

• AIX 7.3 — fsubs (Floating Subtract Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.