Sylpheed/tools/ppc-manual/fpu/fsubx.md

fsubx — Floating Subtract

Category: Floating-Point · Form: A · Opcode: 0xfc000028

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsub	fsubx	—	Floating Subtract
fsub.	fsubx	Rc=1	Floating Subtract

Syntax

fsub[Rc] [FD], [FA], [FB]

Encoding

fsubx — form A

• Opcode word: 0xfc000028
• Primary opcode (bits 0–5): 63
• Extended opcode: 20
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fsubx: read	Source A floating-point register (fr0–fr31).
FB	fsubx: read	Source B floating-point register.
FD	fsubx: write	Destination floating-point register.
CR	fsubx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fsubx: write	Floating-Point Status and Control Register.

Register Effects

fsubx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fsubx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- FRA − FRB

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fsubx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fsubx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:127
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:96
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1036

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fsubx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frA) - (frB)
  Value* v = f.Sub(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Double precision. fsub operates on IEEE-754 binary64. The single-precision sibling is fsubsx, which rounds the result to binary32 before re-encoding it into the 64-bit FPR.
• ±∞ − ±∞ is the canonical invalid case. Same-signed infinity subtraction (or opposite-signed addition) yields QNaN(VXISI) and sets FPSCR[VXISI, VX, FX].
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits OX, UX, XX, VXISI, VXSNAN as appropriate. Canary does not model FPSCR updates (UpdateFPSCR is a stub) — a divergence that almost never matters in practice.
• Rc=1 (fsub.) writes CR1 from FPSCR[FX, FEX, VX, OX].
• NaN propagation. Any NaN operand yields a quiet NaN; a signalling NaN input is quietened (signalling bit cleared) per PowerISA. Host f64 - is relied on for the value.
• Sign of zero. +0 − +0 = +0 in round-to-nearest, −0 in round-toward-negative-infinity. Canary's vsubsd follows the host rounding mode, which it loads from FPSCR[RN].
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.
• Encoding. A-form, primary 63, XO 20. FRC is don't-care for sub.

Related Instructions

• fsubsx — single-precision subtract (rounds to binary32).
• faddx, faddsx — add counterparts; subtract is implemented as add-with-negated-B on most cores.
• fnegx — sign flip (the bit-pattern operation behind −FRB).
• fmsubx, fnmsubx — fused multiply-subtract (single rounding step).
• mffsx, mtfsfx, mtfsb0x, mtfsb1x — FPSCR control.

IBM Reference

• AIX 7.3 — fsub (Floating Subtract)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.