Sylpheed/tools/ppc-manual/vmx/vcmpequw.md

vcmpequw — Vector Compare Equal-to Unsigned Word

Category: VMX (Altivec) · Form: VC · Opcode: 0x10000086

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpequw	vcmpequw	—	Vector Compare Equal-to Unsigned Word
vcmpequw.	vcmpequw	Rc=1	Vector Compare Equal-to Unsigned Word
vcmpequw128	vcmpequw128	—	Vector128 Compare Equal-to Unsigned Word
vcmpequw128.	vcmpequw128	Rc=1	Vector128 Compare Equal-to Unsigned Word

Syntax

vcmpequw[Rc] [VD], [VA], [VB]
vcmpequw128[Rc] [VD], [VA], [VB]

Encoding

vcmpequw — form VC

• Opcode word: 0x10000086
• Primary opcode (bits 0–5): 4
• Extended opcode: 134
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

vcmpequw128 — form VX128_R

• Opcode word: 0x18000200
• Primary opcode (bits 0–5): 6
• Extended opcode: 512
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22–25	XO	extended opcode (compare)
26	VA128h	source A middle bit
27	Rc	record-form flag (updates CR6)
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vcmpequw: read; vcmpequw128: read	Source A vector register.
VB	vcmpequw: read; vcmpequw128: read	Source B vector register.
VD	vcmpequw: write; vcmpequw128: write	Destination vector register.
CR	vcmpequw: write (conditional); vcmpequw128: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpequw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

vcmpequw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpequw: CR6 ← [all-true, 0, all-false, 0] when Rc=1.
• vcmpequw128: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpequw

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpequw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:727
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:327
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:674

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpequw(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxi_(f, i, vcmpxxi_eq, 4, i.VXR.VD, i.VXR.VA, i.VXR.VB,
                            i.VXR.Rc);
}

vcmpequw128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpequw128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:731
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:328
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:800

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpequw128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxi_(f, i, vcmpxxi_eq, 4, VX128_R_VD128, VX128_R_VA128,
                            VX128_R_VB128, i.VX128_R.Rc);
}

Special Cases & Edge Conditions

• Per-word mask: all-ones / all-zero. Four word lanes; VD[i] = (VA[i] == VB[i]) ? 0xFFFFFFFF : 0. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Sign-agnostic. Equality is bit-identical for signed and unsigned words; there is no vcmpeqsw.
• CR6 update when Rc=1 (vcmpequw.). CR6 = [lt = all-true, gt = 0, eq = all-false, so = 0]. Classic "did all four 32-bit hash buckets match?" early-out pattern.
• Compose with vsel. Mask drives vsel per word.
• Common usage. Hashtable probe matching, packed-RGBA pixel comparisons, packed-int handle equality.
• No VSCR interaction, no XER, no traps.
• Aliasing legal.
• VMX128 sibling (vcmpequw128). Identical semantics with the extended encoding; Canary routes both to one body (InstrEmit_vcmpxxi_).

Related Instructions

• vcmpequb, vcmpequh — equality compare at byte / half width.
• vcmpgtuw, vcmpgtsw — > at word width, unsigned / signed.
• vcmpeqfp — same shape, IEEE-754 single-precision equality.
• vsel, vand, vandc, vor, vxor — mask consumers / combinators.
• vspltisw, vspltw — broadcast sources for needle patterns.

IBM Reference

• AIX 7.3 — vcmpequw (Vector Compare Equal-to Unsigned Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares