Sylpheed/tools/ppc-manual/alu/mulhwux.md

mulhwux — Multiply High Word Unsigned

Category: Integer ALU · Form: XO · Opcode: 0x7c000016

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulhwu	mulhwux	—	Multiply High Word Unsigned
mulhwu.	mulhwux	Rc=1	Multiply High Word Unsigned

Syntax

mulhwu[Rc] [RD], [RA], [RB]

Encoding

mulhwux — form XO

• Opcode word: 0x7c000016
• Primary opcode (bits 0–5): 31
• Extended opcode: 11
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulhwux: read	Source GPR (r0–r31).
RB	mulhwux: read	Source GPR.
RD	mulhwux: write	Destination GPR.
CR	mulhwux: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mulhwux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR

Status-Register Effects

• mulhwux: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RT <- high_32_of_unsigned_multiply((RA)[32:63], (RB)[32:63]) zero-extended to 64

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulhwux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mulhwux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:347
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:57
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:862
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:383-393

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mulhwux => {
            // PPCBUG-020: 32-bit ABI CR0 view.
            let ra = ctx.gpr[instr.ra()] as u32 as u64;
            let rb = ctx.gpr[instr.rb()] as u32 as u64;
            let result = ra.wrapping_mul(rb);
            ctx.gpr[instr.rd()] = (result >> 32) & 0xFFFF_FFFF;
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as u32 as i32 as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Inputs are the low 32 bits, zero-extended. RA[32:63] and RB[32:63] are treated as unsigned, widened to 64-bit u64, multiplied; the high 32 bits of the 64-bit product land in RT[32:63]. Xenia masks the high 32 bits of RT to zero (interpreter.rs:231).
• Pair with mullwx for the full 64-bit unsigned product. mullw returns the low 32 sign-extended; for unsigned use, pair mulhwu with rlwinm to mask the low half. Xbox 360 compilers commonly emit this combination.
• No OE bit. Same family rule.
• Rc=1 CR0 update. Uses as i32 as i64 (interpreter.rs:234). Because the result is bounded by 0xFFFFFFFF and stored only in the low 32 bits, this CR0 will report LT for any unsigned high half ≥ 0x80000000 — a known signed/unsigned interpretation pitfall when Rc=1 is used with mulhwu.
• Common idiom for multi-precision arithmetic. mulhwu + mullw + addc chains build extended-precision multiplies entirely in 32-bit ops; useful for cryptographic code that targets the Xenon's 32-bit ABI.
• Multi-cycle latency like the rest of the multiply family.

Related Instructions

• mullwx — low 32 bits of the same product (sign-extended).
• mulhwx — signed high half.
• mulhdux — 64-bit unsigned high half.
• addcx, addex — used to chain 32-bit products into wider precision.

IBM Reference

• AIX 7.3 — mulhwu (Multiply High Word Unsigned)