Sylpheed/tools/ppc-manual/alu/rldclx.md

rldclx — Rotate Left Doubleword then Clear Left

Category: Integer ALU · Form: MDS · Opcode: 0x78000010

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldcl	rldclx	—	Rotate Left Doubleword then Clear Left
rldcl.	rldclx	Rc=1	Rotate Left Doubleword then Clear Left

Syntax

rldcl[Rc] [RA], [RS], [RB], [MB]

Encoding

rldclx — form MDS

• Opcode word: 0x78000010
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	RB	source B GPR
21–26	mb/me	6-bit mask field (swapped halves)
27–30	XO	extended opcode
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldclx: read	Source GPR (alias for RD in some stores).
RB	rldclx: read	Source GPR.
MB	rldclx: read	Mask begin bit.
RA	rldclx: write	Source GPR (r0–r31).
CR	rldclx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldclx

• Reads (always): RS, RB, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldclx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldclx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldclx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:856
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:733
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:802-811

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldclx => {
            let rs = ctx.gpr[instr.rs()];
            let sh = ctx.gpr[instr.rb()] & 0x3F;
            let mb = instr.mb_md();
            let rotated = rs.rotate_left(sh as u32);
            let mask = rld_mask_left(mb);
            ctx.gpr[instr.ra()] = rotated & mask;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL64(RS, RB[58:63]) & MASK(MB, 63). Rotate RS left by RB & 0x3F, then clear bits to the left of MB — i.e. keep bits MB..63, force bits 0..MB-1 to zero.
• Shift comes from a register. Unlike rldiclx, the rotate amount is dynamic. Only the low 6 bits of RB are used (& 0x3F); the upper 58 bits are silently ignored.
• MB is a split 6-bit field. Bit 5 of the encoded mb/me is swapped into bit position 5 (raw bit 30) — xenia decodes via (instr.mb() << 1) | ((raw >> 1) & 1) (interpreter.rs:587). This MDS form is unusual; if you write a decoder, follow this exact bit assembly.
• Mask generation. rld_mask_left(MB) is (1 << (64 - MB)) - 1 — i.e. clear bits 0..MB-1, keep bits MB..63. When MB = 0 the mask is all ones; when MB = 63 only bit 63 survives.
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:592 uses as i64 directly — no truncation. The rotate-and-mask family is one of the few xenia-rs instruction groups that already does the spec-correct 64-bit CR0 compare.
• No XER effect.
• Use over rldiclx when the shift amount is computed at runtime (e.g. via cntlzd for normalisation).

Related Instructions

• rldcrx — sister: clear right instead of left.
• rldiclx, rldicrx, rldicx — immediate-shift variants.
• rldimix — rotate and mask insert.
• rlwnmx, rlwinmx — 32-bit cousins.
• sldx, srdx — preferred for plain 64-bit shifts.

IBM Reference

• AIX 7.3 — rldcl (Rotate Left Doubleword then Clear Left)