Sylpheed/tools/ppc-manual/vmx/vcfsx.md

vcfsx — Vector Convert from Signed Fixed-Point Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000034a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcfs	vcfsx	—	Vector Convert from Signed Fixed-Point Word

Syntax

vcfsx [VD], [VB], [UIMM]

Encoding

vcfsx — form VX

• Opcode word: 0x1000034a
• Primary opcode (bits 0–5): 4
• Extended opcode: 842
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vcfsx: read	Source B vector register.
UIMM	vcfsx: read	16-bit unsigned immediate. Zero-extended.
VD	vcfsx: write	Destination vector register.

Register Effects

vcfsx

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcfsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcfsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:500
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:319
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:624

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcfsx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcfsx_(f, i.VX.VD, i.VX.VB, i.VX.VA);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:489) ──
int InstrEmit_vcfsx_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
                     uint32_t uimm) {
  // (VD) <- float(VB as signed) / 2^uimm
  Value* v = f.VectorConvertI2F(f.LoadVR(vb));
  if (uimm) {
    float fuimm = std::ldexp(1.0f, -int(uimm));
    v = f.Mul(v, f.Splat(f.LoadConstantFloat32(fuimm), VEC128_TYPE));
  }
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Convert signed-Q int32 lane to binary32. For each of the four word lanes, VD[i] = (float)VB[i] / 2^UIMM, where UIMM is the 5-bit immediate at bits 11..15 of the instruction. UIMM ranges 0..31; UIMM=0 is plain integer-to-float.
• Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Use case. Q-format fixed-point (Qm.n) → IEEE float in one instruction. UIMM gives the fractional bit count, so vcfsx vD, vB, 16 interprets each lane as Q15.16.
• Inexact rounding. Values whose magnitude exceeds 2^24 lose mantissa precision (only 24 bits in binary32's significand). The default rounding mode is round-to-nearest-even; VMX has no per-instruction rounding control.
• VSCR[NJ] (flush-denormals) affects the output if the scaled value is sub-normal. Canary converts with vcvtdq2ps and multiplies by 2^-UIMM under its VMX MXCSR, which flushes such results to zero while NJ is set.
• No VSCR[SAT] or XER changes, no exceptions raised.
• No VMX128 sibling.
• Round-trip caveat. vctsxs (the inverse) saturates instead of wrapping, so a vcfsx/vctsxs round-trip is not identity for values outside the signed-int32 representable range — important for fixed-point interpolation kernels.

Related Instructions

• vcfux — same shape, unsigned source.
• vctsxs — inverse: float → signed-Q int32 with saturation.
• vctuxs — inverse: float → unsigned-Q uint32 with saturation.
• vrfin, vrfiz — float-to-integer rounding modes when no Q-format scale is needed.

IBM Reference

• AIX 7.3 — vcfsx (Vector Convert from Signed Fixed-Point Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions