The 3-bit field at +24bit in DWORD 1 of the XMA context was named
subframe_skip_count but never actually used for skipping subframes.
Testing across multiple titles (PGR4, Halo Reach) shows the field
might control extra output buffer blocks that must be reserved per decoded
frame. Renaming the field to output_buffer_padding to reflect this
observed behavior and adding padding to the minimum output space threshold
Pdding blocks are reserved from the output budget after each frame is
fully consumed, preventing the decoder from overrunning the space
that the game expects to remain free.
This is still likely not entirely correct but reduces some of the
observed noise in current implementation.
Drivers and hardware may provide more optimal paths for untyped buffers
compared to typed.
Also, ByteAddressBuffer may be bound via a root descriptor in Direct3D 12,
greatly simplifying the binding logic.
ByteAddressBuffer also doesn't have the 128 * 2^20 element count limit that
typed and structured buffers have, and doesn't require the structure stride
to be specified at resource creation time in Direct3D 11.
The D3D12 backend's existing check only validated the last page of the
range. The Vulkan backend had no check at all and did not respect the
gpu_allow_invalid_upload_range cvar. Both now verify start and
end pages are mapped before copying, preventing access violations when
games reference unmapped guest physical memory during transitions.
"packed" was never set because source_depth_texture isn't created for
stencil bit output. This caused the discard logic to be skipped
resulting in stencil being incorrectly incremented on every transfer
draw until it saturated at 0xFF.
Fixes many remaining Vulkan rendering issues, e.g. Brothers, Orange Box,
Arkham Origins, many others.
Implement SNaN detection and FPSCR exception tracking so that Rc=1 FPU
instructions (fadds., fmadds., etc.) correctly update CR1 with FPSCR
exception summary bits (FX, FEX, VX, OX). Previously these were
hardcoded to zero. Enable ~2k tests that were previously disabled.
Add 3-bit VC field to VX128_2 format structure to support
instructions like vperm128 that use 4 distinct vector operands.
The VC field occupies bits 6-8 of the instruction encoding.
mcrfs: Implement Move CR from FPSCR instruction
Copies a 4-bit FPSCR field to CR and clears the FPSCR exception bits.
mffsx: Fix Rc bit handling
Properly update CR1 from FPSCR when Rc=1 instead of returning error.
Previously treated Rc=1 as unimplemented.
fcfidx: Fix Rc field access
Use i.X.Rc instead of i.A.Rc for correct instruction format.
fcfid uses X format, not A format.
Implement mcrxr (Move to Condition Register from XER).
Copies XER condition bits (SO, OV, CA) to a CR field and
clears those bits in XER. This was previously unimplemented.
Correct mfvscr and mtvscr to use VX format instead of VX128_1.
These instructions operate on the standard Altivec VSCR register,
not VMX128 extended registers. The previous VX128_1 format was
incorrectly accessing the RB field instead of VD/VB.
