xenia-rs/migration/project-root/ppc-manual/alu/srawx.md

srawx — Shift Right Algebraic Word

Category: Integer ALU · Form: X · Opcode: 0x7c000630

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sraw	srawx	—	Shift Right Algebraic Word
sraw.	srawx	Rc=1	Shift Right Algebraic Word

Syntax

sraw[Rc] [RA], [RS], [RB]

Encoding

srawx — form X

• Opcode word: 0x7c000630
• Primary opcode (bits 0–5): 31
• Extended opcode: 792
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srawx: read	Source GPR (alias for RD in some stores).
RB	srawx: read	Source GPR.
RA	srawx: write	Source GPR (r0–r31).
CR	srawx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	srawx: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

srawx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• srawx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS)[32:63] >>a n) sign-extended
CA <- 1 if (signed RS < 0) && any_bit_shifted_out else 0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srawx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="srawx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1262
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:840
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:642-660

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::srawx => {
            // PPCBUG-041+043 coupled: 32-bit ABI writeback truncation + CR0 i32.
            // CA logic is independently correct (uses u32 shifted-out test).
            let rs = ctx.gpr[instr.rs()] as i32;
            let sh = ctx.gpr[instr.rb()] as u32 & 0x3F;
            if sh == 0 {
                ctx.gpr[instr.ra()] = rs as u32 as u64;
                ctx.xer_ca = 0;
            } else if sh < 32 {
                let result = rs >> sh;
                ctx.xer_ca = if rs < 0 && (rs as u32) << (32 - sh) != 0 { 1 } else { 0 };
                ctx.gpr[instr.ra()] = result as u32 as u64;
            } else {
                ctx.gpr[instr.ra()] = if rs < 0 { 0xFFFF_FFFFu64 } else { 0 };
                ctx.xer_ca = if rs < 0 { 1 } else { 0 };
            }
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 32-bit arithmetic right shift, sign-extended to 64. RA ← ((i32)RS >> n) sign-extended, with XER[CA] set when RS[32] = 1 (negative) AND any low bit was shifted out.
• Shift count is 6 bits, RB[58:63]. Counts ≥ 32 saturate: RA = -1 (all-ones, sign-extended) if RS < 0, else 0. Xenia handles this in three branches (interpreter.rs:432-444).
• SH = 0 sign-extends RS to 64 bits and clears XER[CA] — like extsw, but additionally writing CA.
• Result is always sign-extended to 64 bits. RA[0:31] matches the sign of RA[32]. This is the key difference from srwx (zero-extension).
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:443 — but since the result is sign-extended, the low 32 bits' sign matches the full 64-bit sign, so spec and xenia agree here.
• Used with addzex for signed divide by 2^n rounding toward zero.
• No OE bit.

Related Instructions

• srawix — immediate-shift form.
• sradx, sradix — 64-bit arithmetic right shifts.
• srwx — 32-bit logical right shift (no XER[CA]).
• addzex — companion for divide-rounding idiom.
• slwx — left shift.

IBM Reference

• AIX 7.3 — sraw (Shift Right Algebraic Word)