xenia-rs/migration/project-root/ppc-manual/alu/srdx.md

srdx — Shift Right Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000436

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srd	srdx	—	Shift Right Doubleword
srd.	srdx	Rc=1	Shift Right Doubleword

Syntax

srd[Rc] [RA], [RS], [RB]

Encoding

srdx — form X

• Opcode word: 0x7c000436
• Primary opcode (bits 0–5): 31
• Extended opcode: 539
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srdx: read	Source GPR (alias for RD in some stores).
RB	srdx: read	Source GPR.
RA	srdx: write	Source GPR (r0–r31).
CR	srdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

srdx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• srdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) >> n)                       if n < 64 else 0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srdx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="srdx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1161
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:821
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:684-691

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::srdx => {
            let sh = ctx.gpr[instr.rb()] & 0x7F;
            ctx.gpr[instr.ra()] = if sh < 64 {
                ctx.gpr[instr.rs()] >> sh
            } else { 0 };
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 64-bit logical right shift. RA ← RS >> (RB & 0x7F) if the count is < 64, else RA = 0. Bits shifted in from the high end are zero (no sign extension).
• Shift count is 7 bits (RB[57:63]). Counts 64..127 produce zero, not RS >> (count mod 64). Xenia respects this with & 0x7F and an explicit if sh < 64 check (interpreter.rs:472).
• No XER[CA] produced. This is the logical right shift; for arithmetic shift with XER[CA] use sradx.
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:475. Result is non-negative as a signed value (high bit is always cleared by the shift), so CR0 will only ever be EQ or GT.
• No OE bit.
• The srdi simplified mnemonic uses rldiclx instead — rldicl rA, rS, 64-n, n — because it can be combined with masking. srd is for runtime-variable counts.

Related Instructions

• srwx — 32-bit logical right shift.
• sradx, sradix — 64-bit arithmetic right.
• sldx — 64-bit left shift.
• rldiclx — srdi immediate-shift expansion.

IBM Reference

• AIX 7.3 — srd (Shift Right Doubleword)