xenia-rs/migration/project-root/ppc-manual/control/crandc.md

crandc — Condition Register AND with Complement

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000102

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
crandc	crandc	—	Condition Register AND with Complement

Syntax

crandc [CRBD], [CRBA], [CRBB]

Encoding

crandc — form XL

• Opcode word: 0x4c000102
• Primary opcode (bits 0–5): 19
• Extended opcode: 129
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	crandc: read	CR source bit A (0–31).
CRBB	crandc: read	CR source bit B (0–31).
CRBD	crandc: write	CR destination bit (0–31).

Register Effects

crandc

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

crandc

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="crandc"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:361
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:17
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:713

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← CR[CRBA] AND ¬CR[CRBB] — a one-instruction "A and not B" that would otherwise need a complement-then-AND sequence. All other CR bits are preserved.
• Bit-level operands. CRBD, CRBA, CRBB are 5-bit indices into the 32 CR bits (0=CR0.LT, 1=CR0.GT, 2=CR0.EQ, 3=CR0.SO, 4=CR1.LT, …, 31=CR7.SO). They need not lie in the same CR field.
• Identity / corner cases. crandc BT, BA, BA always yields 0 (a clear-bit idiom, equivalent to but slower than crxor BT, BT, BT). crandc BT, BA, BB with BB always 0 reduces to crmove BT, BA.
• Use case. Synthesises "branch if A and not B" predicates without a dedicated cmp of B. Example: branch only if cr0.EQ and not cr1.SO — crandc 2, 2, 7 then beq on cr0.
• No Rc / OE. Pure CR-bit dataflow; doesn't update CR0 or XER.
• Not synchronising. Reorderable.
• xenia status. Interpreter handles via the generic CR-logical helper. xenia-canary's InstrEmit_crandc emits a host AND of A and bitwise-NOT of B.

Related Instructions

• crand, cror, crorc — closest siblings.
• crnand, crnor, crxor, creqv — full set of CR Boolean ops.
• mcrf — copy entire CR field; complementary "broad" CR move.
• bcx — typical consumer of synthesised CR bits.

crandc has no dedicated simplified mnemonic. See crand for the standard crmove / crset / crclr family.

IBM Reference

• AIX 7.3 — crandc (Condition Register AND with Complement)
• AIX 7.3 — Condition register simplified mnemonics