xenia-rs/migration/project-root/ppc-manual/control/crxor.md

crxor — Condition Register XOR

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000182

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
crxor	crxor	—	Condition Register XOR

Syntax

crxor [CRBD], [CRBA], [CRBB]

Encoding

crxor — form XL

• Opcode word: 0x4c000182
• Primary opcode (bits 0–5): 19
• Extended opcode: 193
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	crxor: read	CR source bit A (0–31).
CRBB	crxor: read	CR source bit B (0–31).
CRBD	crxor: write	CR destination bit (0–31).

Register Effects

crxor

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

crxor

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="crxor"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:415
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:17
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:715

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← CR[CRBA] XOR CR[CRBB]. Result is 1 iff the two source bits differ.
• crclr BT idiom. With identical operands, crxor BT, BT, BT always yields 0 (any bit XOR'd with itself is 0). This is the canonical PowerPC clear-to-0 for a single CR bit; assemblers recognise the simplified mnemonic crclr BT. Compilers emit it before variadic-argument calls (PPC ABI uses cr1.SO to flag presence of FP arguments).
• Bit-level operands. Three independent 5-bit absolute CR-bit indices (0..31).
• Use case. Branch on "A != B"; or, with the crclr idiom, zero a CR bit before fall-through CR computation.
• No Rc / OE. No CR0 / XER side effects.
• Not synchronising. Reorderable.
• xenia status. Common enough in real code (typically as crclr 6 for the variadic-FP marker) that translators often special-case the crclr pattern. xenia-canary's InstrEmit_crxor emits a host XOR; xenia-rs decodes via the generic CR-logical handler.

Related Instructions

• creqv — the dual; creqv BT, BT, BT is the standard set-to-1 idiom.
• crand, crandc, crnand — AND family.
• cror, crorc, crnor — OR family.
• mcrf — bulk CR-field copy.
• bcx, bclrx — typical consumers of synthesised CR bits.

Simplified Mnemonics

Simplified	Expansion	Effect
crclr BT	crxor BT, BT, BT	force CR[BT] ← 0

IBM Reference

• AIX 7.3 — crxor (Condition Register XOR)
• AIX 7.3 — Condition register simplified mnemonics