Sylpheed/tools/ppc-manual/alu/andx.md

andx — AND

Category: Integer ALU · Form: X · Opcode: 0x7c000038

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
and	andx	—	AND
and.	andx	Rc=1	AND

Syntax

and[Rc] [RA], [RS], [RB]

Encoding

andx — form X

• Opcode word: 0x7c000038
• Primary opcode (bits 0–5): 31
• Extended opcode: 28
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	andx: read	Source GPR (alias for RD in some stores).
RB	andx: read	Source GPR.
RA	andx: write	Source GPR (r0–r31).
CR	andx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• andx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) & (RB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andx

• Canary XML: tools/ppc-instructions.xml — search for mnem="andx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:637
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:20
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:875

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_andx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) & (RB)
  Value* ra = f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• Operand convention is reversed. Unlike the arithmetic XO-form (add RT, RA, RB), the logical X-form writes RA and reads RS/RB: and RA, RS, RB. The destination is the second operand encoded. This convention applies to the entire and/or/xor family; mixing them up is a frequent disassembly error.
• No OE, no XER[CA], no XER[OV]. Logical operations never affect XER. Only Rc=1 updates CR0 (signed compare against zero, with SO ← XER[SO]).
• 64-bit AND on Xenon. Both inputs are 64-bit GPRs; the result is the bitwise AND of all 64 bits.
• 64-bit CR update on Xenon, 32-bit in Canary. f.UpdateCR(0, v) compares the low 32 bits. For an AND whose high 32 bits are non-zero but low 32 bits are zero (e.g. r3 = 0x1_0000_0000, and. r4, r3, r3), spec sets CR0 to GT but Canary sets EQ. Flag this if reproducing CR-sensitive behaviour.
• Operand aliasing. and RA, RA, RA is a no-op except for the optional CR0 update — this is the canonical "test register against zero" pattern when no cmpwi is desired (though cmpwi is more typical).
• No simplified mnemonic for AND-immediate. Use andix (andi.) or andisx (andis.) for immediate operands; both are always record forms (no plain andi).

Related Instructions

• andcx — AND with complement: RA ← RS & ~RB.
• andix, andisx — D-form AND immediate (always Rc=1).
• nandx — NAND.
• orx, orcx, xorx, eqvx, norx — sister logical instructions.
• cmp, cmpi — explicit zero/value test when CR-only effect is wanted without overwriting RA.

IBM Reference

• AIX 7.3 — and (AND)
• AIX 7.3 — Reference: PowerPC instruction set