Sylpheed/tools/ppc-manual/memory/ld.md

ld — Load Doubleword

Category: Memory · Form: DS · Opcode: 0xe8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ld	ld	—	Load Doubleword
ldu	ldu	—	Load Doubleword with Update
ldux	ldux	—	Load Doubleword with Update Indexed
ldx	ldx	—	Load Doubleword Indexed

Syntax

ld [RD], [ds]([RA0])
ldu [RD], [ds]([RA])
ldux [RD], [RA], [RB]
ldx [RD], [RA0], [RB]

Encoding

ld — form DS

• Opcode word: 0xe8000000
• Primary opcode (bits 0–5): 58
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

ldu — form DS

• Opcode word: 0xe8000001
• Primary opcode (bits 0–5): 58
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

ldux — form X

• Opcode word: 0x7c00006a
• Primary opcode (bits 0–5): 31
• Extended opcode: 53
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

ldx — form X

• Opcode word: 0x7c00002a
• Primary opcode (bits 0–5): 31
• Extended opcode: 21
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	ld: read; ldx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
ds	ld: read; ldu: read	14-bit signed word-aligned displacement (DS << 2).
RD	ld: write; ldu: write; ldux: write; ldx: write	Destination GPR.
RA	ldu: read; ldu: write; ldux: read; ldux: write	Source GPR (r0–r31).
RB	ldux: read; ldx: read	Source GPR.

Register Effects

ld

• Reads (always): RA0, ds
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

ldu

• Reads (always): RA, ds
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

ldux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

ldx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(ds || 0b00)
RT <- MEM(EA, 8)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ld

• Canary XML: tools/ppc-instructions.xml — search for mnem="ld"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:347
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:106
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:495

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ld(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(DS || 0b00)
  // RT <- MEM(EA, 8)
  Value* b;
  if (i.DS.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.DS.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.DS.DS << 2));
  Value* rt = f.ByteSwap(f.LoadOffset(b, offset, INT64_TYPE));
  f.StoreGPR(i.DS.RT, rt);
  return 0;
}

ldu

• Canary XML: tools/ppc-instructions.xml — search for mnem="ldu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:367
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:109
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:496

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ldu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(DS || 0b00)
  // RT <- MEM(EA, 8)
  // RA <- EA
  Value* ea = CalculateEA_i(f, i.DS.RA, XEEXTS16(i.DS.DS << 2));
  Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
  f.StoreGPR(i.DS.RT, rt);
  StoreEA(f, i.DS.RA, ea);
  return 0;
}

ldux

• Canary XML: tools/ppc-instructions.xml — search for mnem="ldux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:378
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:110
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:879

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ldux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // RT <- MEM(EA, 8)
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
  f.StoreGPR(i.X.RT, rt);
  StoreEA(f, i.X.RA, ea);
  return 0;
}

ldx

• Canary XML: tools/ppc-instructions.xml — search for mnem="ldx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:389
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:111
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:870

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ldx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- MEM(EA, 8)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• DS-form, not D-form. The displacement is 14 bits scaled by 4 (EXTS(ds || 0b00)), giving a signed range of ±32 KiB in 4-byte steps. Bits 30–31 are the extended opcode used to distinguish ld (XO=0) from ldu (XO=1). The assembler accepts a normal byte displacement and verifies divisibility by 4.
• Big-endian read. The 64 bits at EA..EA+7 form the loaded value, most-significant byte first. Xenia-rs's mem.read_u64 returns the host-native value of that big-endian doubleword.
• No zero/sign-extension question. ld already fills the entire 64-bit register; there is no lda (load doubleword algebraic) — the doubleword is the architectural maximum.
• RA0 (non-update forms). RA = 0 in ld and ldx means base is literal zero. ld RT, 0x100(0) reads from absolute 0x100.
• Update-form invalid forms. ldu / ldux invoke "RA = 0" and "RA = RT" as invalid forms. AIX docs say results are undefined; xenia performs the read first, then writes back RA ← EA, which would silently destroy the loaded value if RA == RT.
• Alignment. Xenon does not enforce doubleword alignment for ld itself — unaligned 8-byte loads are tolerated. However, real POWER cores may take an alignment exception on some implementations; portable code keeps doublewords 8-byte aligned.
• 64-bit pointer / counter loads. Although Xbox 360 user code is 32-bit, kernel structures and TOC entries are doublewords; ld is the standard load for them.

Related Instructions

• lwz, lhz, lbz — narrower zero-extending loads.
• lwa, lha — sign-extending loads (no lda exists; ld already fills the register).
• ldbrx — byte-reversed doubleword load.
• ldarx / stdcx — load-reserve / store-conditional doubleword pair.
• std, stdu, stdx, stdux — corresponding stores.

IBM Reference

• AIX 7.3 — ld (Load Doubleword)
• AIX 7.3 — ldu / ldux / ldx