Sylpheed/tools/ppc-manual/memory/lbz.md

lbz — Load Byte and Zero

Category: Memory · Form: D · Opcode: 0x88000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lbz	lbz	—	Load Byte and Zero
lbzu	lbzu	—	Load Byte and Zero with Update
lbzux	lbzux	—	Load Byte and Zero with Update Indexed
lbzx	lbzx	—	Load Byte and Zero Indexed

Syntax

lbz [RD], [d]([RA0])
lbzu [RD], [d]([RA])
lbzux [RD], [RA], [RB]
lbzx [RD], [RA0], [RB]

Encoding

lbz — form D

• Opcode word: 0x88000000
• Primary opcode (bits 0–5): 34
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lbzu — form D

• Opcode word: 0x8c000000
• Primary opcode (bits 0–5): 35
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lbzux — form X

• Opcode word: 0x7c0000ee
• Primary opcode (bits 0–5): 31
• Extended opcode: 119
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lbzx — form X

• Opcode word: 0x7c0000ae
• Primary opcode (bits 0–5): 31
• Extended opcode: 87
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lbz: read; lbzx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lbz: read; lbzu: read	16-bit signed displacement (d) added to the base address register.
RD	lbz: write; lbzu: write; lbzux: write; lbzx: write	Destination GPR.
RA	lbzu: read; lbzu: write; lbzux: read; lbzux: write	Source GPR (r0–r31).
RB	lbzux: read; lbzx: read	Source GPR.

Register Effects

lbz

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

lbzu

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lbzux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lbzx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
RT <- 0x00000000_000000_00 || MEM(EA, 1)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lbz

• Canary XML: tools/ppc-instructions.xml — search for mnem="lbz"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:72
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:101
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:472

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lbz(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // RT <- i56.0 || MEM(EA, 1)
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt = f.ZeroExtend(f.LoadOffset(b, offset, INT8_TYPE), INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  return 0;
}

lbzu

• Canary XML: tools/ppc-instructions.xml — search for mnem="lbzu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:92
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:102
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:473

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lbzu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // RT <- i56.0 || MEM(EA, 1)
  // RA <- EA
  Value* ra = f.LoadGPR(i.D.RA);
  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt = f.ZeroExtend(f.LoadOffset(ra, offset, INT8_TYPE), INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  StoreEA(f, i.D.RA, f.Add(ra, offset));
  return 0;
}

lbzux

• Canary XML: tools/ppc-instructions.xml — search for mnem="lbzux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:104
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:103
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:891

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lbzux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // RT <- i56.0 || MEM(EA, 1)
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  Value* rt = f.ZeroExtend(f.Load(ea, INT8_TYPE), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  StoreEA(f, i.X.RA, ea);
  return 0;
}

lbzx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lbzx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:115
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:104
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:889

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lbzx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- i56.0 || MEM(EA, 1)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.ZeroExtend(f.Load(ea, INT8_TYPE), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Single-byte read. The smallest scalar load. No endian concerns at the byte level — MEM(EA, 1) returns the literal byte at address EA, regardless of host or target byte order.
• Zero-extension to 64 bits. The high 56 bits of RT become zero. Use lha / lhax family for sign-extending byte-equivalent semantics; there is no PowerPC "load byte sign-extended" — you must lbz then extsb (or use lha on a half).
• RA0 (non-update forms). When RA = 0 in lbz / lbzx, the base is the literal zero, so lbz RT, 0x4000(0) reads from absolute address 0x4000. Update forms lbzu / lbzux invoke RA = 0 (and RA = RT) as invalid forms; xenia's interpreter does not check, so well-formed compiler output is assumed.
• Update-form post-write. lbzu / lbzux write the computed EA back to RA after the load; the snapshot first reads, then assigns RA ← EA, matching IBM's "the load and update happen as one operation" wording.
• No alignment requirement. A byte load is intrinsically aligned. Xenon does not raise alignment exceptions for any byte access.
• Common in string and table-lookup code. Most uses are character-string scans, jump-table dispatches, and packed-bool reads. Compilers also use lbz to materialise small immediate constants stored in .rodata.

Related Instructions

• lhz, lwz, ld — wider zero-extending loads in the same family.
• lha, lwa — sign-extending siblings (no lba exists; use lbz + extsb).
• stb, stbu, stbx, stbux — the corresponding stores.
• lwbrx, lhbrx — byte-reversed multi-byte loads (no byte-equivalent needed).
• lmw, lswi, lswx — multi-word / string loads for bulk transfer.

IBM Reference

• AIX 7.3 — lbz (Load Byte and Zero)
• AIX 7.3 — lbzu (Load Byte and Zero with Update)