Sylpheed/tools/ppc-manual/memory/sth.md

sth — Store Half Word

Category: Memory · Form: D · Opcode: 0xb0000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sth	sth	—	Store Half Word
sthu	sthu	—	Store Half Word with Update
sthux	sthux	—	Store Half Word with Update Indexed
sthx	sthx	—	Store Half Word Indexed

Syntax

sth [RS], [d]([RA0])
sthu [RS], [d]([RA])
sthux [RS], [RA], [RB]
sthx [RS], [RA0], [RB]

Encoding

sth — form D

• Opcode word: 0xb0000000
• Primary opcode (bits 0–5): 44
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

sthu — form D

• Opcode word: 0xb4000000
• Primary opcode (bits 0–5): 45
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

sthux — form X

• Opcode word: 0x7c00036e
• Primary opcode (bits 0–5): 31
• Extended opcode: 439
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

sthx — form X

• Opcode word: 0x7c00032e
• Primary opcode (bits 0–5): 31
• Extended opcode: 407
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sth: read; sthu: read; sthux: read; sthx: read	Source GPR (alias for RD in some stores).
RA0	sth: read; sthx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	sth: read; sthu: read	16-bit signed displacement (d) added to the base address register.
RA	sthu: read; sthu: write; sthux: read; sthux: write	Source GPR (r0–r31).
RB	sthux: read; sthx: read	Source GPR.

Register Effects

sth

• Reads (always): RS, RA0, d
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

sthu

• Reads (always): RS, RA, d
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

sthux

• Reads (always): RS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

sthx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
MEM(EA, 2) <- (RS)[48:63]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sth

• Canary XML: tools/ppc-instructions.xml — search for mnem="sth"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:455
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:247
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:482

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sth(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // MEM(EA, 2) <- (RS)[48:63]
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  f.StoreOffset(b, offset,
                f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT16_TYPE)));
  return 0;
}

sthu

• Canary XML: tools/ppc-instructions.xml — search for mnem="sthu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:475
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:249
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:483

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sthu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // MEM(EA, 2) <- (RS)[48:63]
  // RA <- EA
  Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT16_TYPE)));
  StoreEA(f, i.D.RA, ea);
  return 0;
}

sthux

• Canary XML: tools/ppc-instructions.xml — search for mnem="sthux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:485
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:250
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:923

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sthux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // MEM(EA, 2) <- (RS)[48:63]
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE)));
  StoreEA(f, i.X.RA, ea);
  return 0;
}

sthx

• Canary XML: tools/ppc-instructions.xml — search for mnem="sthx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:495
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:251
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:921

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sthx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 2) <- (RS)[48:63]
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE)));
  return 0;
}

Special Cases & Edge Conditions

• Stores low 16 bits of RS. Writes (RS)[48:63] — the low half-word — at EA. The xenia snapshot does mem.write_u16(ea, ctx.gpr[instr.rs()] as u16). The high 48 bits of RS are ignored: storing a 64-bit value through sth silently truncates.
• Big-endian write. Byte at EA is the high byte of the half (RS[48:55]), byte at EA+1 is the low byte (RS[56:63]). On little-endian hosts the byte-swap happens at the memory boundary.
• RA0 (non-update forms). RA = 0 in sth and sthx selects literal zero. Update forms sthu / sthux invoke RA = 0 as an invalid form.
• Update-form post-write. sthu / sthux write the computed EA back to RA after the store.
• No alignment requirement. Xenon tolerates unaligned half-word stores; the two bytes are written at EA and EA+1 regardless of alignment.
• Common in audio / Unicode code. Standard store for 16-bit PCM samples and UTF-16 code units. Compilers emit sth for short * writes.
• Cache effects. A sth to a cold line triggers a read-allocate; for bulk half-word writes to a fresh line, prefer pre-clearing with dcbz128.

Related Instructions

• stb, stw, std — narrower / wider stores.
• sthbrx — byte-reversed half-word store (little-endian half).
• lhz, lha — corresponding loads (zero / sign extension).
• stmw, stswi, stswx — bulk stores.

IBM Reference

• AIX 7.3 — sth (Store Half)
• AIX 7.3 — sthu / sthx / sthux