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dc3de9dbc4
docs: map IDXD reflective framework; defaulted-field routes
iterate-4A/apu-xma-stage1
MechaCat02
2026-07-09 22:09:28 +02:00
f51c7c8ca9
docs: add message\ scheme + labeling coverage to RE symbol map
MechaCat02
2026-07-09 21:57:08 +02:00
6b248d71e9
docs: RE symbol map + DB re-stamp for cracked IPFB name-hash
MechaCat02
2026-07-09 21:45:26 +02:00
5950dc86d5
[iterate-4A] jit: coverage — update-form loads/stores + mfspr/mtspr(LR/CTR) → 89.6% native
MechaCat02
2026-07-08 07:06:42 +02:00
0becc9185a
[iterate-4A] jit: coverage — cheap integer ALU ops (+5pt native, chain -14% vs interp)
MechaCat02
2026-07-08 06:33:01 +02:00
e3cc6d11d0
[iterate-4A] jit: per-block GPR register caching — bodies now beat interp
MechaCat02
2026-07-08 06:15:16 +02:00
4b78c67605
[iterate-4A] jit: superblock chaining B2 — bcx two-way + loop back-edges
MechaCat02
2026-07-07 21:25:21 +02:00
2c17a511f7
[iterate-4A] jit: native superblock chaining B1 (bx + fall-through), −6.4% wall
MechaCat02
2026-07-07 20:55:12 +02:00
5d5dc5dd89
[iterate-4A] jit: cache MemEnv fast_mem + expose mmio_count (prep for block chaining)
MechaCat02
2026-07-07 20:02:05 +02:00
da0509b4ac
[iterate-4A] jit: inline load fast-path (skip trampoline) — JIT reaches interpreter parity
MechaCat02
2026-07-07 19:44:56 +02:00
d91311c486
[iterate-4A] jit: FP arithmetic via interpreter-punt (diff-clean, 73.48% native)
MechaCat02
2026-07-07 19:18:06 +02:00
704e87a2a4
[iterate-4A] jit: FP-move tier — lfs/stfs/lfd/stfd + fmr/fabs/fneg (diff-clean, 39.82% native)
MechaCat02
2026-07-07 19:09:15 +02:00
6475f4ba97
[iterate-4A] jit: memory tier — integer loads/stores via trampolines (diff-clean, 38.78% native)
MechaCat02
2026-07-07 18:57:19 +02:00
15d0d7e0bd
[iterate-4A] jit: cover integer ALU + compares w/ CR emission (diff-clean, 22% native)
MechaCat02
2026-07-07 07:36:49 +02:00
56dbf52a5f
[iterate-4A] jit: wire compiled-block cache + cover bx/bcx/bclrx (diff-clean, 6.57% native)
MechaCat02
2026-07-07 07:28:26 +02:00
cc7ff58cb0
[iterate-4A] jit: Cranelift block-JIT scaffolding + addi/addis PoC (pipeline proven)
MechaCat02
2026-07-06 20:45:31 +02:00
07cd272412
[iterate-4A] jit: opcode-frequency histogram (XENIA_JIT_HIST) for coverage targeting
MechaCat02
2026-07-06 20:36:53 +02:00
ac289bca5e
[iterate-4A] jit M0: recompiler seam + in-process differential harness
MechaCat02
2026-07-06 20:25:18 +02:00
e07f93ed0a
[iterate-4A] perf: superblock budget 128->192 (movie-validated ~7% wall) + profiler attribution
MechaCat02
2026-07-06 19:45:23 +02:00
cc9ebbb5e7
[iterate-4A] docs: handoff for intro-video-done milestone + speed frontier
MechaCat02
2026-07-03 07:45:11 +02:00
2c883e9d5e
[iterate-4A] diagnostics: XENIA_PROFILE wall-time profiler + probe/tooling snapshot
MechaCat02
2026-07-03 07:43:53 +02:00
5573ac1c43
[iterate-4A] intro-video: correct MULSC/ADDSC/SUBSC operand addressing
intro-video-done
MechaCat02
2026-07-02 21:58:40 +02:00
deb9292395
[iterate-4A] intro-video: complete RectangleList quad (fix diagonal seam)
MechaCat02
2026-07-02 20:53:37 +02:00
3559c8f6ef
[iterate-4A] intro-video ROOT #3 : render the YUV movie in correct color
MechaCat02
2026-07-02 20:23:56 +02:00
43441523f9
[iterate-4A] intro-video: re-baseline boot golden 50M -> 200M after clock fix
MechaCat02
2026-07-01 20:39:38 +02:00
645feb8f5b
[iterate-4A] intro-video: fix decode-timeout clock, feeder starvation, k_8 texture decode
MechaCat02
2026-07-01 20:34:01 +02:00
3e17d37b4e
[iterate-4A] intro-video RE: XENIA_AUDIT_PC_TRACE (per-tid PC-range r3/r4/r5/r30/r31 trace)
MechaCat02
2026-06-28 21:17:27 +02:00
7e9ee1ac33
intro-video RE: deep demux-core instrumentation + handoff hygiene
MechaCat02
2026-06-26 07:54:15 +02:00
23189b95af
[iterate-4A] Milestone-2: XMA audio decoder + RE tooling (dispatch recorder, analyzer vtable-fix, non-perturbing probes)
MechaCat02
2026-06-21 21:38:19 +02:00
acb29db444
[iterate-3AL] Superblock dispatch: chain basic blocks per slot-visit (~1.6x boot-to-splash)
iterate-3O/real-render-slice
MechaCat02
2026-06-19 22:31:54 +02:00
dc1320cd4b
[iterate-3AK] Perf quick-wins: ~21% faster boot-to-splash (22→27 MIPS)
MechaCat02
2026-06-19 22:05:53 +02:00
9d24dd0eaa
[iterate-3AJ] Present-anchor vsync so the splash logo fade-in renders
MechaCat02
2026-06-19 21:01:33 +02:00
c62a355418
[iterate-3AE] Fix spurious WHITE TRIANGLE flashing before each splash logo
MechaCat02
2026-06-19 14:09:54 +02:00
3f8d3b6f1c
[iterate-3AD] Fix 2nd splash logo rendering black: re-upload evolving atlas
MechaCat02
2026-06-19 13:38:35 +02:00
c0c6088e4d
[iterate-3AA] Fix logo upside-down: no Y-flip on the clip-enabled NDC path
MechaCat02
2026-06-18 21:18:30 +02:00
f6f3aac673
[iterate-3Z] Fix logo color (yellow->white): k_8_8_8_8 vfetch + vfetch field/stride/saturate
MechaCat02
2026-06-18 20:58:21 +02:00
2a992db47b
[iterate-3Y] Replay per-draw blend + write-mask so the logo composites visible
MechaCat02
2026-06-18 19:53:25 +02:00
89b5c39d8a
[iterate-3X] Real splash logo geometry renders: fix vertex-fetch const_index_sel + per-draw submit
MechaCat02
2026-06-18 19:25:50 +02:00
39723dfe37
[iterate-3W] draw_capture: walk CF exec sequence to find the real vertex fetch
MechaCat02
2026-06-18 18:50:13 +02:00
da7c29b6d2
[iterate-3V] Fix logo texture: map texture-fetch physical base onto backing window
MechaCat02
2026-06-18 18:07:00 +02:00
1b9918450f
[iterate-3T] Real UV interpolation + per-draw textures: shader/UV/bind chain complete
MechaCat02
2026-06-18 17:12:16 +02:00
80fbff8bd1
[iterate-3S] Real splash geometry renders: fix ALU/vfetch decode + per-draw NDC transform
MechaCat02
2026-06-18 16:35:01 +02:00
6d8a2817a3
[iterate-3R] Fix --ui boot throttle: demote idle-advance scheduler log to DEBUG
MechaCat02
2026-06-18 15:47:16 +02:00
a3aa3cc7d6
[iterate-3Q] draw_capture: read vertex window via physical alias
MechaCat02
2026-06-18 15:28:49 +02:00
6ff184694d
[iterate-3P] Real splash geometry in --ui: fix CF predication decode + translator op coverage
MechaCat02
2026-06-18 15:07:06 +02:00
504592ac13
[iterate-3O] Real-render slice: replay guest geometry in --ui (Route A)
MechaCat02
2026-06-17 22:38:46 +02:00
6bb4355e3d
[iterate-3M] Fix Xenos shader CF/fetch decode so the textured logo binds
iterate-3M/logo-item-texture
MechaCat02
2026-06-17 21:53:35 +02:00
3f5d5cf5f7
[iterate-2Z] Implement NtSetInformationFile FileRenameInformation for cache: files
master
iterate-2Z/idx2-logo-load
MechaCat02
2026-06-15 21:33:25 +02:00
2f55d1fd7d
[iterate-2X] Texture pipeline: un-stub RectangleList + draw-time texture decode
iterate-2X/texture-logo
MechaCat02
2026-06-14 21:34:43 +02:00
a91f4c550b
[iterate-2W] Sustain the title present loop: viewport-size register + ISR CPU impersonation
iterate-2W/per-present-interrupt
MechaCat02
2026-06-14 20:49:32 +02:00
66bd805726
[iterate-2V] VdSwap: stop bumping primary CP_RB_WPTR out-of-band (canary-faithful)
iterate-2V/vdswap-no-wptr-bump
MechaCat02
2026-06-14 19:58:05 +02:00
ad9c8e4cb8
[iterate-2U] VdGlobalDevice: allocate a real device cell so the swap counter (clock B) can advance
iterate-2U/vdglobaldevice-cell
MechaCat02
2026-06-14 16:20:08 +02:00
873c197ff1
[iterate-2T] VdSwap: route present through ring PM4_XE_SWAP, drop out-of-band swap interrupt
iterate-2T/vdswap-present-interrupt
MechaCat02
2026-06-14 15:20:02 +02:00
1ae472bd2b
[iterate-2S] GPU: implement CP SCRATCH_REG memory writeback — arms Sylpheed's swap-callback slot
iterate-2S/swap-callback-arm
MechaCat02
2026-06-14 14:21:30 +02:00
034ec8b47f
[iterate-2O] GPU: drain indirect buffers correctly — Sylpheed renders splash (draws 0→78)
iterate-2Q/vblank-swap-producer
iterate-2P/texture-decode-resolve
iterate-2O/gpu-syscmdbuf-drain
MechaCat02
2026-06-13 22:06:16 +02:00
93f60a3ba0
[iterate-2M] PCR+0x10C (PRCB.current_cpu): init per-HW-thread to unwedge spin-barrier
iterate-2M/pcr-current-cpu
MechaCat02
2026-06-13 18:08:46 +02:00
2bdb93e51e
[iterate-2K] GPU physical-mirror aliasing: ring/IB/RPtr/resolve read wrong host region
iterate-2K/physical-mirror-aliasing
MechaCat02
2026-06-13 13:39:57 +02:00
ed2e0e72fd
[iterate-2J] KeTimeStampBundle deterministic tick: fix frozen+mislaid guest clock
iterate-2J/timestamp-bundle-tick
MechaCat02
2026-06-13 11:54:44 +02:00
f75bc96d17
[iterate-2H] PPC spin/yield/sync hint-class audit: lock no-over-yield + barrier-decode invariants
iterate-2I/worker-0x109c
MechaCat02
2026-06-13 10:53:54 +02:00
de21c7a544
[iterate-2G] db16cyc spin-hint cooperative yield: unblock title-screen 0x10a0 gate
MechaCat02
2026-06-13 10:38:17 +02:00
f3b7e8b760
[iterate-2F] Scheduler anti-starvation floor: fix job-4 handoff render gate
MechaCat02
2026-06-13 10:02:02 +02:00
7e2603a9e5
[iterate-2E] Extend coherent monotonic clock to lockstep (timebase-desync livelock fix)
MechaCat02
2026-06-12 21:42:28 +02:00
5aaadfec36
[iterate-2E] Add XENIA_AUDIT_DEREF pointer-chase probe
MechaCat02
2026-06-12 20:29:01 +02:00
0332d1990d
[Track 2] Parallel-scoped global clock fixes timebase-desync livelock
MechaCat02
2026-06-12 19:32:14 +02:00
6271ba1f55
chore: gitignore vkd3d-proton/DXVK runtime shader caches
MechaCat02
2026-06-12 18:06:25 +02:00
48b19e490f
[Prong A] Three 32-bit ABI PPCBUG siblings corrected to canary semantics
MechaCat02
2026-06-12 17:25:41 +02:00
341196a111
[Issue-1 PPCBUG-020] Word-form ALU ops produce full 64-bit results
MechaCat02
2026-06-12 16:21:11 +02:00
b20c99f141
[Subsystem-fixes] 6 verified ours-vs-canary divergence fixes
MechaCat02
2026-06-12 14:57:38 +02:00
db90ad0f7d
[AUDIT-059 R-D2] Phase D auto-signal POC confirms audit-049 wedge diagnosis
MechaCat02
2026-06-11 18:38:38 +02:00
481591fdb2
[AUDIT-059 R-C1] Phase C: bit-28 setter hypothesis REFUTED via dump-addr
MechaCat02
2026-06-11 17:57:27 +02:00
52c30d82a7
[AUDIT-059 R-A] Phase A backward-trace: divergence is sub_822F1AA8 loop exit, not factory/registry
MechaCat02
2026-06-11 17:02:20 +02:00
229b46c765
[Kernel] Slab-recycle handle allocator (AUDIT-059 R34)
iterate-2BG/slab-recycle-handles
MechaCat02
2026-06-10 18:04:34 +02:00
40f208ea4e
[2.BF] Silph WorkerCtx: install canary's real sub-vtable at [+0x2C][0]
iterate-2BF/synthetic-silph-spawn
MechaCat02
2026-06-07 21:19:52 +02:00
8683fb59ed
[2.BF] Silph WorkerCtx: synthesize sub-object + vtable at [+0x2C]
MechaCat02
2026-06-07 21:04:04 +02:00
b5885b8560
[2.BF] Synthetic silph::WorkerCtx spawn (round 18 — opt-in landing)
MechaCat02
2026-06-07 20:44:29 +02:00
9340ff4592
[Audit] --audit-r3-dump-bytes: dump N bytes at r3 when probe fires
audit-2BF/sub82172BA0-bctrl-probe
MechaCat02
2026-06-07 19:39:22 +02:00
bcd018659b
[Audit] --audit-mem-dump-chain: deref a guest address N levels for diagnosis
MechaCat02
2026-06-07 12:13:42 +02:00
09e59e09b7
Audit-2BF.delta: add --audit-pc-probe-hex for silph-init bctrl probe
MechaCat02
2026-06-07 10:59:03 +02:00
5a8fe21ad5
Iterate-2.BF.γ: refine is_in_callback gate to per-thread exclusion
iterate-2BE/host-driven-isr-delivery
MechaCat02
2026-06-06 19:52:16 +02:00
51489e34db
Iterate-2.BE Path β: tick vsync from coord_idle_advance
MechaCat02
2026-06-06 19:22:03 +02:00
9a93152981
Iterate-2.BE: host-driven synchronous graphics ISR delivery
MechaCat02
2026-06-06 18:58:40 +02:00
a4926c73f4
docs: handoff report for continuing on another machine
handoff/2026-06-05-continue-elsewhere
MechaCat02
2026-06-05 07:21:32 +02:00
d293f1bcaf
wip(probe): throwaway iterate-iterate-2AT-deref probe instrumentation
iterate-2AT-deref
MechaCat02
2026-06-05 07:19:28 +02:00
d6acb21b2e
wip(probe): throwaway iterate-iterate-2AU-xaudio probe instrumentation
iterate-2AU-xaudio
MechaCat02
2026-06-05 07:19:28 +02:00
bc37074f9e
wip(probe): throwaway iterate-iterate-2AZ-vsync probe instrumentation
iterate-2AZ-vsync
MechaCat02
2026-06-05 07:19:28 +02:00
ef93a4fa14
handoff: VSync/event-wedge fixes + iterate 2.A–2.BC research notes
chore/portable-snapshot
MechaCat02
2026-06-05 07:19:08 +02:00
acd1656753
WEDGE-PROGRESSION: deadline-fire + nt_create_event polarity
worktree-agent-a0848e51cc0d72503
MechaCat02
2026-06-02 19:43:18 +02:00
ad45873a1b
ITERATE-2.V: scheduler priority aging closes 18-day AUDIT-049 wedge
MechaCat02
2026-05-29 07:27:26 +02:00
e6d43a23ac
chore: add migration/ bundle for cross-machine setup
MechaCat02
2026-05-10 21:38:38 +02:00
8e709b0a24
chore: track audit-runs summary artifacts (md/csv/diff/txt/json/etc)
MechaCat02
2026-05-10 21:36:41 +02:00
609f586ed8
chore: backfill audit-findings.md with entries from audits 023-057
MechaCat02
2026-05-10 21:35:21 +02:00
ac2f89a7bb
Re-baseline sylpheed_n50m golden post-AUDIT-054
MechaCat02
2026-05-10 18:11:11 +02:00
2a8ff9515d
AUDIT-054: thread CreateOptions through NtCreateFile + opt-in cache persistence
MechaCat02
2026-05-10 18:11:04 +02:00
25704c5811
Re-baseline sylpheed_n50m golden post-AUDIT-032
MechaCat02
2026-05-10 15:07:40 +02:00
49f3eafa15
AUDIT-032: dedicated audio worker thread per client (Plan B)
MechaCat02
2026-05-10 15:06:25 +02:00
7bc9e3acac
Merge analysis-overhaul/vmx-stores (M9.5 + M11.5 + VMX + SJIS/UTF-8)
MechaCat02
2026-05-10 00:36:53 +02:00
e428ce33aa
M9.5 + M11.5 + VMX + SJIS/UTF-8: close the post-M5.5 deferred set
MechaCat02
2026-05-10 00:36:53 +02:00
b03192c772
Merge analysis-overhaul/m5.5-this-flow
MechaCat02
2026-05-09 23:35:05 +02:00
56ffa40a6a
M5.5: this-flow indirect-dispatch resolution via vptr-write inference
MechaCat02
2026-05-09 23:35:05 +02:00
d8766c6242
Merge vfs-cache-persistent/p0-real-disk-backing — audit-038 cache fix
MechaCat02
2026-05-09 14:34:34 +02:00